CPU Design Verification Engineer
$141K - $172K/yr
Description As a CPU Design Verification Engineer owning the verification of a certain area of ... formal Should be a great teammate with excellent communication skills and be able to work ...
$141K - $172K/yr
Description As a CPU Design Verification Engineer owning the verification of a certain area of ... formal Should be a great teammate with excellent communication skills and be able to work ...
$141K - $172K/yr
Description As a CPU Design Verification Engineer owning the verification of a certain area of ... formal Should be a great teammate with excellent communication skills and be able to work ...
Beaverton, OR · On-site
$141K - $172K/yr
Description As a CPU Design Verification Engineer owning the verification of a certain area of ... formal Should be a great teammate with excellent communication skills and be able to work ...
Beaverton, OR · On-site
$141K - $172K/yr
Description As a CPU Design Verification Engineer owning the verification of a certain area of ... formal Should be a great teammate with excellent communication skills and be able to work ...
Beaverton, OR · On-site
$141K - $172K/yr
Description As a CPU Design Verification Engineer owning the verification of a certain area of ... formal Should be a great teammate with excellent communication skills and be able to work ...
Beaverton, OR · On-site
$141K - $172K/yr
Description As a CPU Design Verification Engineer owning the verification of a certain area of ... formal Should be a great teammate with excellent communication skills and be able to work ...
Beaverton, OR · On-site
$141K - $172K/yr
Description As a CPU Design Verification Engineer owning the verification of a certain area of ... formal Should be a great teammate with excellent communication skills and be able to work ...
Beaverton, OR · On-site
$141K - $172K/yr
Description As a CPU Design Verification Engineer owning the verification of a certain area of ... formal Should be a great teammate with excellent communication skills and be able to work ...
$141K - $172K/yr
Description As a CPU Design Verification Engineer owning the verification of a certain area of ... formal Should be a great teammate with excellent communication skills and be able to work ...
$141K - $172K/yr
Description As a CPU Design Verification Engineer owning the verification of a certain area of ... formal Should be a great teammate with excellent communication skills and be able to work ...
$141K - $172K/yr
Description As a CPU Design Verification Engineer owning the verification of a certain area of ... formal Should be a great teammate with excellent communication skills and be able to work ...
$141K - $172K/yr
Description As a CPU Design Verification Engineer owning the verification of a certain area of ... formal Should be a great teammate with excellent communication skills and be able to work ...
Beaverton, OR · On-site
$141K - $172K/yr
Description As a CPU Design Verification Engineer owning the verification of a certain area of ... formal Should be a great teammate with excellent communication skills and be able to work ...
Beaverton, OR · On-site
$141K - $172K/yr
Description As a CPU Design Verification Engineer owning the verification of a certain area of ... formal Should be a great teammate with excellent communication skills and be able to work ...
Beaverton, OR · On-site
$140 - $190/hr
Description As a CPU Design Verification Engineer owning the verification of a certain area of ... Experience with advanced verification techniques such as formal * Should be a great teammate with ...
Beaverton, OR · On-site
$140 - $190/hr
Description As a CPU Design Verification Engineer owning the verification of a certain area of ... Experience with advanced verification techniques such as formal * Should be a great teammate with ...
$148K - $180K/yr
... formal verification approaches, to validate complex SoC designs. - Develop and execute block ... Qualifications: Minimum Qualifications - Bachelor's or BS degree in Electrical Engineering ...
$148K - $180K/yr
... formal verification approaches, to validate complex SoC designs. - Develop and execute block ... Qualifications: Minimum Qualifications - Bachelor's or BS degree in Electrical Engineering ...
$184K - $324K/yr
Design Verification Engineers at Apple are responsible for verifying the functionality and ... for formal education related to advancing your career at Apple, reimbursement for certain ...
$184K - $324K/yr
Design Verification Engineers at Apple are responsible for verifying the functionality and ... for formal education related to advancing your career at Apple, reimbursement for certain ...
$184K - $324K/yr
Design Verification Engineers at Apple are responsible for verifying the functionality and ... for formal education related to advancing your career at Apple, reimbursement for certain ...
$184K - $324K/yr
Design Verification Engineers at Apple are responsible for verifying the functionality and ... for formal education related to advancing your career at Apple, reimbursement for certain ...
$184K - $324K/yr
Design Verification Engineers at Apple are responsible for verifying the functionality and ... for formal education related to advancing your career at Apple, reimbursement for certain ...
$184K - $324K/yr
Design Verification Engineers at Apple are responsible for verifying the functionality and ... for formal education related to advancing your career at Apple, reimbursement for certain ...
Tualatin, OR · On-site
$154K - $247K/yr
Master's Degree or equivalent in Electrical Engineering/Computer Engineering/Computer Science or ... Static and/or dynamic Formal Verification * Experience with GVP source control continuous ...
Tualatin, OR · On-site
$154K - $247K/yr
Master's Degree or equivalent in Electrical Engineering/Computer Engineering/Computer Science or ... Static and/or dynamic Formal Verification * Experience with GVP source control continuous ...
Master's Degree or equivalent in Electrical Engineering/Computer Engineering/Computer Science or ... Static and/or dynamic Formal Verification * Experience with GVP source control continuous ...
Master's Degree or equivalent in Electrical Engineering/Computer Engineering/Computer Science or ... Static and/or dynamic Formal Verification * Experience with GVP source control continuous ...
Our researchers apply formal analysis techniques to the design and verification of critical ... Research Engineers at Galois design and develop advanced technologies for safety- and security ...
Our researchers apply formal analysis techniques to the design and verification of critical ... Research Engineers at Galois design and develop advanced technologies for safety- and security ...
Portland, OR · On-site
Our researchers apply formal analysis techniques to the design and verification of critical ... Research Engineers at Galois design and develop advanced technologies for safety- and security ...
Quick apply
Portland, OR · On-site
Our researchers apply formal analysis techniques to the design and verification of critical ... Research Engineers at Galois design and develop advanced technologies for safety- and security ...
Portland, OR · On-site
Our researchers apply formal analysis techniques to the design and verification of critical ... Research Engineers at Galois design and develop advanced technologies for safety- and security ...
Portland, OR · On-site
Our researchers apply formal analysis techniques to the design and verification of critical ... Research Engineers at Galois design and develop advanced technologies for safety- and security ...
... formal verification • Work with the implementation/CAD teams during the entire chip design cycle to drive signoff closure for tapeout • Work with the SOC team to meet IP technical and delivery ...
... formal verification • Work with the implementation/CAD teams during the entire chip design cycle to drive signoff closure for tapeout • Work with the SOC team to meet IP technical and delivery ...
... formal verification • Work with the implementation/CAD teams during the entire chip design cycle to drive signoff closure for tapeout • Work with the SOC team to meet IP technical and delivery ...
... formal verification • Work with the implementation/CAD teams during the entire chip design cycle to drive signoff closure for tapeout • Work with the SOC team to meet IP technical and delivery ...
$129K - $194K/yr
Preferred Qualifications Experienced with physical verification flows such as DRC/LVS/ANT and ... for formal education related to advancing your career at Apple, reimbursement for certain ...
$129K - $194K/yr
Preferred Qualifications Experienced with physical verification flows such as DRC/LVS/ANT and ... for formal education related to advancing your career at Apple, reimbursement for certain ...
$84.6K - $96.5K
1% of jobs
$96.5K - $108.3K
1% of jobs
$108.3K - $120.2K
1% of jobs
$120.2K - $132.1K
1% of jobs
$139.1K is the 25th percentile. Wages below this are outliers.
$132.1K - $143.9K
35% of jobs
The median wage is $146.3K / yr.
$143.9K - $155.8K
54% of jobs
$155.8K - $167.7K
1% of jobs
$167.7K - $179.5K
1% of jobs
$179.5K - $191.4K
2% of jobs
$191.4K - $203.3K
1% of jobs
$203.3K - $215.2K
1% of jobs
$84.6K
$150.8K
$215.2K
To thrive as a Formal Verification Engineer, you need a strong background in digital design, computer architecture, and logic, typically supported by a degree in electrical engineering, computer science, or a related field. Expertise in formal verification tools such as Cadence JasperGold, Synopsys VC Formal, or Mentor Questa, along with proficiency in hardware description languages (HDLs) like Verilog or VHDL, is essential. Strong analytical thinking, attention to detail, and effective communication skills help you collaborate with design and verification teams and present complex findings. These competencies are critical for ensuring hardware systems are bug-free, reliable, and meet stringent industry standards.
As a Formal Verification Engineer, your typical day involves creating and analyzing formal properties, developing assertions, and using formal verification tools to mathematically prove correctness of hardware designs. You'll collaborate closely with design and simulation teams to review specifications, identify verification requirements, and debug issues found during the verification process. Regular documentation of findings, participation in code and design reviews, and ongoing learning about new verification methodologies are also important parts of the role. This dynamic environment requires both technical depth and proactive teamwork to ensure high-quality design outcomes.
A Formal Verification Engineer is responsible for ensuring the correctness of hardware or software designs using mathematical and logical techniques. They apply formal methods to verify that a system behaves as intended, identifying potential design flaws early in the development process. This involves writing formal properties, using model checking tools, and collaborating with design and validation teams. Their work helps improve reliability, reduce bugs, and enhance the efficiency of verification compared to traditional simulation-based methods.

8.0
Based on 677 frontline employees who took The Breakroom Quiz
7th of 30 rated technology retailers
Sourced by ZipRecruiter
Imagine what you could do here! At Apple, new ideas have a way of becoming extraordinary products, services, and customer experiences very quickly. Bring passion and dedication to your job and there's no telling what you could accomplish. Dynamic, intelligent people and inspiring, innovative technologies are the norm here. The people who work here have reinvented entire industries with all Apple Hardware products. The same real passion for innovation that goes into our products also applies to our practices strengthening our dedication to leave the world better than we found it.
Computer and electronic product manufacturing
10,000+ Employees
Cupertino, CA, US
1976