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Dft Engineer Jobs in Arizona (NOW HIRING)

RTL Design Engineer

Chandler, AZ · On-site

$127K - $203K/yr

  • Medical

  • Dental

  • Vision

  • Retirement

  • PTO

Broadcom's Central Engineering Group is seeking a candidate to lead the digital design and ... Experience with Tessent tool for DFT insertion and verification * Proficient with Perl, Python and ...

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Industrial Painters

Eloy, AZ · On-site

$22 - $26/hr

  • Medical

  • Dental

  • Vision

  • Life

  • Retirement

  • PTO

... with engineering specifications, customer finish requirements, and the company's ISO 9001:2015 ... thickness (DFT) range, using proper overlapping spray technique, gun speed, and gun-to-part ...

Principal Electrical Engineer

Phoenix, AZ · On-site

$130K - $159K/yr

Drive designformanufacturability (DFM), designforassembly (DFA), and designfortest (DFT) efforts ... Partner with crossfunctional engineering teams to ensure integrated, robust hardware solutions ...

Senior Substrate Layout Engineer

Phoenix, AZ · On-site

$97K - $134K/yr

... designfortest (DFT) considerations * Coordinate development processes to ensure alignment with ... Bachelor's or higher degree in engineering in electrical or electronics engineering * Typically ...

... designfortest (DFT) considerations * Coordinate development processes to ensure alignment with ... Bachelor's or higher degree in engineering in electrical or electronics engineering * Typically ...

IP Verification Engineer

Chandler, AZ · Hybrid

$130K - $176K/yr

Our Solution Engineering division is seeking a skilled verification engineer to develop testbenches ... DFT methodologies: RTL testability, scan insertion, OCC In Return: We are proud to have a set of ...

The Coating Field Engineer serves as the primary technical interface between engineering ... Familiarity with coating inspection methods including DFT measurement, environmental monitoring ...

Principal Electrical Engineer

Phoenix, AZ · On-site

$130K - $159K/yr

Drive design-for-manufacturability (DFM), design-for-assembly (DFA), and design-for-test (DFT ... Partner with cross-functional engineering teams to ensure integrated, robust hardware solutions ...

Senior Substrate Layout Engineer

Phoenix, AZ · On-site

$97K - $134K/yr

... test (DFT) considerations * Coordinate development processes to ensure alignment with supplier ... Bachelor's or higher degree in engineering in electrical or electronics engineering * Typically ...

Our Solution Engineering division is seeking a skilled verification engineer to develop testbenches ... DFT methodologies: RTL testability, scan insertion, OCC In Return: We are proud to have a set of ...

Our Solution Engineering division is seeking a skilled verification engineer to develop testbenches ... DFT methodologies: RTL testability, scan insertion, OCC In Return: We are proud to have a set of ...

Showing results 41-60

Dft Engineer information

See Arizona salary details

$68K

$120.7K

$232K

How much do dft engineer jobs pay per year?

As of Aug 15, 2026, the average yearly pay for dft engineer in Arizona is $120,690.00, according to ZipRecruiter salary data. Most workers in this role earn between $96,000.00 and $125,300.00 per year, depending on experience, location, and employer.

What are the key skills and qualifications needed to thrive as a DFT engineer?

To thrive as a DFT (Design for Test) Engineer, you need a solid background in electrical engineering, digital design, and ASIC/FPGA development, often supported by a relevant degree. Familiarity with test methodologies, scan insertion tools (such as Synopsys DFT Compiler or Mentor Tessent), and scripting languages like Perl or Python is typically required. Strong problem-solving skills, attention to detail, and effective communication help DFT Engineers collaborate with design and verification teams to resolve complex testability challenges. These competencies are essential to ensure high-quality, testable silicon designs that minimize defects and streamline manufacturing processes.

What is the difference between Dft Engineer vs Test Engineer?

AspectDft EngineerTest Engineer
Required CredentialsBachelor's in Electronics, Electrical, or related fields; certifications in DFT techniquesBachelor's in Electronics, Electrical, Computer Science; certifications in testing methodologies
Work EnvironmentDesign and implementation of DFT strategies during IC developmentTesting, validation, and debugging of electronic products and systems
Employer & Industry UsageSemiconductor companies, IC design firmsConsumer electronics, automotive, telecommunications industries

While both Dft Engineers and Test Engineers work in electronics and semiconductor industries, Dft Engineers focus on designing testability features during chip development, whereas Test Engineers execute testing and validation of finished products. Their roles complement each other, but their daily tasks and expertise areas differ significantly.

Is DFT engineering a good career?

DFT (Design for Test) engineering is a specialized field within semiconductor and integrated circuit design, focusing on ensuring chip testability and manufacturability. It offers steady demand due to the need for quality control in electronics manufacturing and typically requires knowledge of digital design, testing methodologies, and tools like EDA software. Career growth depends on industry trends, technical skills, and certifications, making it a viable option for those interested in hardware design and testing.

How much do DFT engineers make?

Design for Test (DFT) engineers typically earn between $80,000 and $130,000 annually, depending on experience, location, and industry. Senior DFT engineers with specialized skills in automation and verification can earn higher salaries, especially in high-demand tech regions.

What does a Dft engineer do?

A DFT (Design for Test) engineer designs and implements testing strategies to ensure integrated circuits and electronic systems are defect-free and function correctly. They develop test plans, create test hardware and software, and work closely with design teams to improve testability and reduce manufacturing defects. Proficiency in scripting, testing tools, and industry standards is essential for this role.

What are some common challenges faced by DFT engineers during the silicon validation phase, and how can these be addressed?

DFT Engineers often encounter challenges during the silicon validation phase, such as discrepancies between simulation results and actual silicon behavior, limited access to internal nodes, and diagnosing scan chain failures. These issues can be addressed by thorough pre-silicon verification, incorporating robust test points, and leveraging advanced diagnostic tools and methodologies. Effective collaboration with design and validation teams is also crucial to quickly resolve issues and implement necessary design changes, ensuring high test coverage and product reliability.

What is a DFT engineer?

DFT Engineers, or Design for Test Engineers, are professionals who specialize in designing and implementing test structures and methodologies within integrated circuits (ICs) to ensure their testability and reliability during manufacturing. Their work enables efficient detection and diagnosis of faults in chips, helping to improve yield and reduce production costs. DFT Engineers collaborate closely with design, verification, and manufacturing teams to integrate features such as scan chains, built-in self-test (BIST), and boundary scan into chip designs. Their expertise is crucial for modern semiconductor development, especially as chips become increasingly complex.

What are the most commonly searched types of Dft Engineer jobs in Arizona?

The most popular types of Dft Engineer jobs in Arizona are:

What job categories do people searching Dft Engineer jobs in Arizona look for?

The top searched job categories for Dft Engineer jobs in Arizona are:

What cities in Arizona are hiring for Dft Engineer jobs?

Cities in Arizona with the most Dft Engineer job openings:

Infographic showing various Dft Engineer job openings in Arizona as of August 2026, with employment types broken down into 92% Full Time, 3% Part Time, and 5% Contract. Highlights an 86% Physical, 5% Hybrid, and 9% Remote job distribution, with an average salary of $120,690 per year, or $58 per hour.

Staff Engineer, Digital Design Engineering (AI/ML)

Analogdevices

Chandler, AZ • On-site

Full-time

Re-posted 20 hours ago


Job description

About Analog Devices

Analog Devices, Inc. (NASDAQ: ADI) is a global semiconductor leader that bridges the physical and digital worlds to enable breakthroughs at the Intelligent Edge. ADI combines analog, digital, AI, and software technologies into solutions that combat climate change, reliably connect humans and the world, and help drive advancements in automation and robotics, mobility, healthcare, energy and data centers. With revenue of more than $11 billion in FY25, ADI ensures today's innovators stay Ahead of What's Possible. Learn more at www.analog.comand on LinkedIn and X.

As a Staff Digital Design Engineer, you will develop complex digital subsystems within ADI's mixed-signal and power management ICs. You will apply AI/ML techniques to improve design automation, optimization, and productivity across the digital design flow. Your work will contribute to products spanning multiple business units, directly supporting how ADI integrates advanced digital functionality into next-generation products.

Key Responsibilities
  • Apply AI/ML methodologies to improve synthesis results, timing closure, power estimation, and design space exploration
  • Develop and implement digital subsystems for mixed-signal ICs, including control logic, digital interfaces, and on-chip processing blocks
  • Execute RTL design, coding, and optimization in Verilog/SystemVerilog for performance, area, and power targets
  • Perform synthesis with timing and placement constraints (Genus), static timing analysis and power analysis (Tempus), and logical equivalence checking (Conformal)
  • Participate in architecture and design reviews, contributing technical analysis on timing, area, power, and testability trade-offs
  • Collaborate with analog design teams to implement and integrate digital-analog interfaces and control architectures
Required Skills and Experience
  • MSEE or MSCE with 7+ years of digital IC design experience, or PhD with 5+ years (BSEE/BSCE with equivalent depth considered)
  • Strong RTL design skills in Verilog/SystemVerilog with experience delivering complex digital subsystems
  • Demonstrated ability to deliver digital designs through tape-out, silicon validation, and production release
  • Solid scripting skills (Python, Tcl, shell) with experience applying AI/ML techniques to enhance productivity
  • Knowledge of synthesis, static timing analysis, DFT (scan, ATPG, BIST), and clock domain crossing methodologies
  • Proficiency with Cadence digital design tools: Genus, Innovus, Tempus, Conformal
  • Excellent presentation, technical writing, and communication skills
Preferred Qualifications
  • Curiosity and initiative to explore AI/ML techniques and emerging tools that can transform design workflows, with an enthusiasm for discovering more effective ways of working
  • Working knowledge of place-and-route (Innovus), floorplanning, and physical-aware design techniques
  • Experience with low-power design techniques including multi-voltage domains, power gating, and UPF
  • Familiarity with digital interfaces (I2C, SPI, UART) and mixed-signal SoC integration
  • Strong analytical and problem-solving abilities
Technical Scope
  • Application of AI/ML-driven workflows to improve design quality, turnaround time, or coverage
  • Block-level digital subsystem ownership from specification through silicon bring-up and production validation
  • Clock domain crossing analysis, lint, and formal verification for multi-clock digital architectures
  • DFT implementation including scan insertion, ATPG pattern generation, and fault coverage closure
Collaboration and Impact
  • Share AI/ML-driven improvements to digital design workflows and best practices with team members
  • Work with analog design, verification, and applications teams to implement digital control architectures that meet system-level requirements
  • Contribute to design reviews and cross-team technical discussions

For positions requiring access to technical data, Analog Devices, Inc. may have to obtain export licensing approval from the U.S. Department of Commerce - Bureau of Industry and Security and/or the U.S. Department of State - Directorate of Defense Trade Controls. As such, applicants for this position - except US Citizens, US Permanent Residents, and protected individuals as defined by 8 U.S.C. 1324b(a)(3) - may have to go through an export licensing review process.

Analog Devices is an equal opportunity employer. We foster a culture where everyone has an opportunity to succeed regardless of their race, color, religion, age, ancestry, national origin, social or ethnic origin, sex, sexual orientation, gender, gender identity, gender expression, marital status, pregnancy, parental status, disability, medical condition, genetic information, military or veteran status, union membership, and political affiliation, or any other legally protected group.

EEO is the Law: Notice of Applicant Rights Under the Law.

Job Req Type: ExperiencedRequired Travel: Yes, 10% of the timeShift Type: 1st Shift/Days