As a Staff Digital Design Engineer, you will develop complex digital subsystems within ADI's mixed ... Knowledge of synthesis, static timing analysis, DFT (scan, ATPG, BIST), and clock domain crossing ...
As a Staff Digital Design Engineer, you will develop complex digital subsystems within ADI's mixed ... Knowledge of synthesis, static timing analysis, DFT (scan, ATPG, BIST), and clock domain crossing ...
RTL Design Engineer
Chandler, AZ · On-site
$127K - $203K/yr
Medical
Dental
Vision
Retirement
PTO
Broadcom's Central Engineering Group is seeking a candidate to lead the digital design and ... Experience with Tessent tool for DFT insertion and verification * Proficient with Perl, Python and ...
RTL Design Engineer
Chandler, AZ · On-site
$127K - $203K/yr
Medical
Dental
Vision
Retirement
PTO
Broadcom's Central Engineering Group is seeking a candidate to lead the digital design and ... Experience with Tessent tool for DFT insertion and verification * Proficient with Perl, Python and ...
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Industrial Painters
Eloy, AZ · On-site
$22 - $26/hr
Medical
Dental
Vision
Life
Retirement
PTO
... with engineering specifications, customer finish requirements, and the company's ISO 9001:2015 ... thickness (DFT) range, using proper overlapping spray technique, gun speed, and gun-to-part ...
Quick apply
Be Seen First
Industrial Painters
Eloy, AZ · On-site
$22 - $26/hr
Medical
Dental
Vision
Life
Retirement
PTO
... with engineering specifications, customer finish requirements, and the company's ISO 9001:2015 ... thickness (DFT) range, using proper overlapping spray technique, gun speed, and gun-to-part ...
Principal Electrical Engineer
Phoenix, AZ · On-site
$130K - $159K/yr
Drive designformanufacturability (DFM), designforassembly (DFA), and designfortest (DFT) efforts ... Partner with crossfunctional engineering teams to ensure integrated, robust hardware solutions ...
Principal Electrical Engineer
Phoenix, AZ · On-site
$130K - $159K/yr
Drive designformanufacturability (DFM), designforassembly (DFA), and designfortest (DFT) efforts ... Partner with crossfunctional engineering teams to ensure integrated, robust hardware solutions ...
Senior Substrate Layout Engineer
Phoenix, AZ · On-site
$97K - $134K/yr
... designfortest (DFT) considerations * Coordinate development processes to ensure alignment with ... Bachelor's or higher degree in engineering in electrical or electronics engineering * Typically ...
Senior Substrate Layout Engineer
Phoenix, AZ · On-site
$97K - $134K/yr
... designfortest (DFT) considerations * Coordinate development processes to ensure alignment with ... Bachelor's or higher degree in engineering in electrical or electronics engineering * Typically ...
Senior Substrate Layout Engineer
$97K - $134K/yr
... designfortest (DFT) considerations * Coordinate development processes to ensure alignment with ... Bachelor's or higher degree in engineering in electrical or electronics engineering * Typically ...
Senior Substrate Layout Engineer
$97K - $134K/yr
... designfortest (DFT) considerations * Coordinate development processes to ensure alignment with ... Bachelor's or higher degree in engineering in electrical or electronics engineering * Typically ...
IP Verification Engineer
Chandler, AZ · Hybrid
$130K - $176K/yr
Our Solution Engineering division is seeking a skilled verification engineer to develop testbenches ... DFT methodologies: RTL testability, scan insertion, OCC In Return: We are proud to have a set of ...
IP Verification Engineer
Chandler, AZ · Hybrid
$130K - $176K/yr
Our Solution Engineering division is seeking a skilled verification engineer to develop testbenches ... DFT methodologies: RTL testability, scan insertion, OCC In Return: We are proud to have a set of ...
Coating Field Engineer
Chandler, AZ · On-site
The Coating Field Engineer serves as the primary technical interface between engineering ... Familiarity with coating inspection methods including DFT measurement, environmental monitoring ...
Coating Field Engineer
Chandler, AZ · On-site
The Coating Field Engineer serves as the primary technical interface between engineering ... Familiarity with coating inspection methods including DFT measurement, environmental monitoring ...
Senior Analog Design Engineer
Chandler, AZ · On-site
$198K/yr
Partner with Design-for-Test engineers to support DFT strategy and implementation. * Lead silicon debugging, characterization, and laboratory evaluation activities for assigned designs. * Collaborate ...
Senior Analog Design Engineer
Chandler, AZ · On-site
$198K/yr
Partner with Design-for-Test engineers to support DFT strategy and implementation. * Lead silicon debugging, characterization, and laboratory evaluation activities for assigned designs. * Collaborate ...
Senior Analog Design Engineer
Chandler, AZ · On-site
$198K/yr
Partner with Design-for-Test engineers to support DFT strategy and implementation. * Lead silicon debugging, characterization, and laboratory evaluation activities for assigned designs. * Collaborate ...
Quick apply
Senior Analog Design Engineer
Chandler, AZ · On-site
$198K/yr
Partner with Design-for-Test engineers to support DFT strategy and implementation. * Lead silicon debugging, characterization, and laboratory evaluation activities for assigned designs. * Collaborate ...
Electrical Engineer I-III
Tucson, AZ · On-site
... DFT) principles • Drive innovation and product enhancements across lifecycle stages • Support audits, quality investigations, and regulatory compliance initiatives Qualifications • Bachelor ...
Electrical Engineer I-III
Tucson, AZ · On-site
... DFT) principles • Drive innovation and product enhancements across lifecycle stages • Support audits, quality investigations, and regulatory compliance initiatives Qualifications • Bachelor ...
Senior Analog Design Engineer
Chandler, AZ · On-site
$198K/yr
Partner with Design-for-Test engineers to support DFT strategy and implementation. * Lead silicon debugging, characterization, and laboratory evaluation activities for assigned designs. * Collaborate ...
Senior Analog Design Engineer
Chandler, AZ · On-site
$198K/yr
Partner with Design-for-Test engineers to support DFT strategy and implementation. * Lead silicon debugging, characterization, and laboratory evaluation activities for assigned designs. * Collaborate ...
Principal Electrical Engineer
Phoenix, AZ · On-site
$130K - $159K/yr
Drive design-for-manufacturability (DFM), design-for-assembly (DFA), and design-for-test (DFT ... Partner with cross-functional engineering teams to ensure integrated, robust hardware solutions ...
Principal Electrical Engineer
Phoenix, AZ · On-site
$130K - $159K/yr
Drive design-for-manufacturability (DFM), design-for-assembly (DFA), and design-for-test (DFT ... Partner with cross-functional engineering teams to ensure integrated, robust hardware solutions ...
Senior Substrate Layout Engineer
Phoenix, AZ · On-site
$97K - $134K/yr
... test (DFT) considerations * Coordinate development processes to ensure alignment with supplier ... Bachelor's or higher degree in engineering in electrical or electronics engineering * Typically ...
Senior Substrate Layout Engineer
Phoenix, AZ · On-site
$97K - $134K/yr
... test (DFT) considerations * Coordinate development processes to ensure alignment with supplier ... Bachelor's or higher degree in engineering in electrical or electronics engineering * Typically ...
Staff Package Design Engineer
Tempe, AZ · On-site
Collaborate with SI/PI, thermal, reliability, DFT, silicon design, product engineering, and manufacturing teams to support package-level co-optimization and participate in design reviews. * Ensure ...
Quick apply
Staff Package Design Engineer
Tempe, AZ · On-site
Collaborate with SI/PI, thermal, reliability, DFT, silicon design, product engineering, and manufacturing teams to support package-level co-optimization and participate in design reviews. * Ensure ...
Senior IP Verification Engineer
Chandler, AZ · On-site
$161K - $218K/yr
Our Solution Engineering division is seeking a skilled verification engineer to develop testbenches ... DFT methodologies: RTL testability, scan insertion, OCC In Return: We are proud to have a set of ...
Senior IP Verification Engineer
Chandler, AZ · On-site
$161K - $218K/yr
Our Solution Engineering division is seeking a skilled verification engineer to develop testbenches ... DFT methodologies: RTL testability, scan insertion, OCC In Return: We are proud to have a set of ...
Senior IP Verification Engineer
Chandler, AZ · Hybrid
$161K - $218K/yr
Our Solution Engineering division is seeking a skilled verification engineer to develop testbenches ... DFT methodologies: RTL testability, scan insertion, OCC In Return: We are proud to have a set of ...
Senior IP Verification Engineer
Chandler, AZ · Hybrid
$161K - $218K/yr
Our Solution Engineering division is seeking a skilled verification engineer to develop testbenches ... DFT methodologies: RTL testability, scan insertion, OCC In Return: We are proud to have a set of ...
Senior Test Engineer
Chandler, AZ · On-site
As a Senior Test Engineer , you will have the opportunity to research product technical ... Knowledge of ATPG, scan chain insertion and DFT development * Excellent communication skills
Quick apply
Senior Test Engineer
Chandler, AZ · On-site
As a Senior Test Engineer , you will have the opportunity to research product technical ... Knowledge of ATPG, scan chain insertion and DFT development * Excellent communication skills
Staff Package Design Engineer
Tempe, AZ · On-site
Collaborate with SI/PI, thermal, reliability, DFT, silicon design, product engineering, and manufacturing teams to support package-level co-optimization and participate in design reviews. * Ensure ...
Staff Package Design Engineer
Tempe, AZ · On-site
Collaborate with SI/PI, thermal, reliability, DFT, silicon design, product engineering, and manufacturing teams to support package-level co-optimization and participate in design reviews. * Ensure ...
Oversee high-level verification planning, DFT strategy, and lab evaluation in partnership with applications and test engineering teams to ensure designs are production-ready. * Drive the ...
Oversee high-level verification planning, DFT strategy, and lab evaluation in partnership with applications and test engineering teams to ensure designs are production-ready. * Drive the ...
Dft Engineer information
See Arizona salary details
$68K - $82.9K
10% of jobs
$94.9K is the 25th percentile. Wages below this are outliers.
$82.9K - $97.8K
19% of jobs
$97.8K - $112.8K
17% of jobs
The median wage is $114.4K / yr.
$112.8K - $127.7K
39% of jobs
$127.7K - $142.6K
12% of jobs
$142.6K - $157.5K
1% of jobs
$157.5K - $172.4K
1% of jobs
$172.4K - $187.3K
1% of jobs
$187.3K - $202.2K
0% of jobs
$202.2K - $217.1K
0% of jobs
$217.1K - $232K
0% of jobs
$68K
$120.7K
$232K
How much do dft engineer jobs pay per year?
What are the key skills and qualifications needed to thrive as a DFT engineer?
What is the difference between Dft Engineer vs Test Engineer?
| Aspect | Dft Engineer | Test Engineer |
|---|---|---|
| Required Credentials | Bachelor's in Electronics, Electrical, or related fields; certifications in DFT techniques | Bachelor's in Electronics, Electrical, Computer Science; certifications in testing methodologies |
| Work Environment | Design and implementation of DFT strategies during IC development | Testing, validation, and debugging of electronic products and systems |
| Employer & Industry Usage | Semiconductor companies, IC design firms | Consumer electronics, automotive, telecommunications industries |
While both Dft Engineers and Test Engineers work in electronics and semiconductor industries, Dft Engineers focus on designing testability features during chip development, whereas Test Engineers execute testing and validation of finished products. Their roles complement each other, but their daily tasks and expertise areas differ significantly.
Is DFT engineering a good career?
How much do DFT engineers make?
What does a Dft engineer do?
What are some common challenges faced by DFT engineers during the silicon validation phase, and how can these be addressed?
What is a DFT engineer?
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The most popular types of Dft Engineer jobs in Arizona are:
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For Dft Engineer jobs in Arizona, the most frequently searched job titles are:
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The top searched job categories for Dft Engineer jobs in Arizona are:
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Cities in Arizona with the most Dft Engineer job openings:

Full-time
Re-posted 20 hours ago
Job description
About Analog Devices
Analog Devices, Inc. (NASDAQ: ADI) is a global semiconductor leader that bridges the physical and digital worlds to enable breakthroughs at the Intelligent Edge. ADI combines analog, digital, AI, and software technologies into solutions that combat climate change, reliably connect humans and the world, and help drive advancements in automation and robotics, mobility, healthcare, energy and data centers. With revenue of more than $11 billion in FY25, ADI ensures today's innovators stay Ahead of What's Possible. Learn more at www.analog.comand on LinkedIn and X.
As a Staff Digital Design Engineer, you will develop complex digital subsystems within ADI's mixed-signal and power management ICs. You will apply AI/ML techniques to improve design automation, optimization, and productivity across the digital design flow. Your work will contribute to products spanning multiple business units, directly supporting how ADI integrates advanced digital functionality into next-generation products.
Key Responsibilities- Apply AI/ML methodologies to improve synthesis results, timing closure, power estimation, and design space exploration
- Develop and implement digital subsystems for mixed-signal ICs, including control logic, digital interfaces, and on-chip processing blocks
- Execute RTL design, coding, and optimization in Verilog/SystemVerilog for performance, area, and power targets
- Perform synthesis with timing and placement constraints (Genus), static timing analysis and power analysis (Tempus), and logical equivalence checking (Conformal)
- Participate in architecture and design reviews, contributing technical analysis on timing, area, power, and testability trade-offs
- Collaborate with analog design teams to implement and integrate digital-analog interfaces and control architectures
- MSEE or MSCE with 7+ years of digital IC design experience, or PhD with 5+ years (BSEE/BSCE with equivalent depth considered)
- Strong RTL design skills in Verilog/SystemVerilog with experience delivering complex digital subsystems
- Demonstrated ability to deliver digital designs through tape-out, silicon validation, and production release
- Solid scripting skills (Python, Tcl, shell) with experience applying AI/ML techniques to enhance productivity
- Knowledge of synthesis, static timing analysis, DFT (scan, ATPG, BIST), and clock domain crossing methodologies
- Proficiency with Cadence digital design tools: Genus, Innovus, Tempus, Conformal
- Excellent presentation, technical writing, and communication skills
- Curiosity and initiative to explore AI/ML techniques and emerging tools that can transform design workflows, with an enthusiasm for discovering more effective ways of working
- Working knowledge of place-and-route (Innovus), floorplanning, and physical-aware design techniques
- Experience with low-power design techniques including multi-voltage domains, power gating, and UPF
- Familiarity with digital interfaces (I2C, SPI, UART) and mixed-signal SoC integration
- Strong analytical and problem-solving abilities
- Application of AI/ML-driven workflows to improve design quality, turnaround time, or coverage
- Block-level digital subsystem ownership from specification through silicon bring-up and production validation
- Clock domain crossing analysis, lint, and formal verification for multi-clock digital architectures
- DFT implementation including scan insertion, ATPG pattern generation, and fault coverage closure
- Share AI/ML-driven improvements to digital design workflows and best practices with team members
- Work with analog design, verification, and applications teams to implement digital control architectures that meet system-level requirements
- Contribute to design reviews and cross-team technical discussions
For positions requiring access to technical data, Analog Devices, Inc. may have to obtain export licensing approval from the U.S. Department of Commerce - Bureau of Industry and Security and/or the U.S. Department of State - Directorate of Defense Trade Controls. As such, applicants for this position - except US Citizens, US Permanent Residents, and protected individuals as defined by 8 U.S.C. 1324b(a)(3) - may have to go through an export licensing review process.
Analog Devices is an equal opportunity employer. We foster a culture where everyone has an opportunity to succeed regardless of their race, color, religion, age, ancestry, national origin, social or ethnic origin, sex, sexual orientation, gender, gender identity, gender expression, marital status, pregnancy, parental status, disability, medical condition, genetic information, military or veteran status, union membership, and political affiliation, or any other legally protected group.
EEO is the Law: Notice of Applicant Rights Under the Law.
Job Req Type: ExperiencedRequired Travel: Yes, 10% of the timeShift Type: 1st Shift/Days