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Design Verification Engineer Startup Jobs (NOW HIRING)

Senior Design Verification Engineer

Austin, TX · On-site

$134.80K - $164.50K/yr

Senior Design Verification Engineer ID: 1061 Location: Austin, TX More about this job > Description Senior Design Verification Engineer Looking for new challenges? Would you like the variety of a ...

We're hiring experienced Design Verification Engineers from junior to senior levels to play a key role in developing and verifying the designs that will bring our next-generation AI processors to ...

We're hiring experienced Design Verification Engineers from junior to senior levels to play a key role in developing and verifying the designs that will bring our next-generation AI processors to ...

Design Verification Engineer

Austin, TX · On-site

$120K - $225K/yr

We're hiring experienced Design Verification Engineers from junior to senior levels to play a key role in developing and verifying the designs that will bring our next-generation AI processors to ...

Design Verification Engineer

Palo Alto, CA · On-site

$120K - $225K/yr

We're hiring experienced Design Verification Engineers from junior to senior levels to play a key role in developing and verifying the designs that will bring our next-generation AI processors to ...

Design Verification Engineer

San Diego, CA · On-site

$144.40K - $176.20K/yr

As a Design Verification Engineer, you'll be at the center of our silicon design group's verification efforts, ensuring the quality and reliability of next-generation cellular systems. Working on ...

Design Verification Engineer

San Diego, CA · On-site

$144.40K - $176.20K/yr

As a Design Verification Engineer, you'll be at the center of our silicon design group's verification efforts, ensuring the quality and reliability of next-generation cellular systems. Working on ...

Senior Design Verification Engineer

San Diego, CA

$144.40K - $176.20K/yr

Design Verification Engineer Duration: Full time or Contract Location: Bay Area, CA About Us: We are representing Sivaltech, A design services company headquartered in Milpitas, CA. We provide ...

GPU Design Verification Engineer Position Description : Protingent Staffing has an exciting contract GPU Design Verification Engineer opportunity with our client located in San Jose, CA. * We are ...

Design Verification Engineer

Irvine, CA · On-site

$146.10K - $178.40K/yr

Design Verification Engineer Location: Santa Clara, CA Duration: 06 months (High Possibility of an extension) Senior DV engineer responsible for defining and implementing verification methodology and ...

Design Verification Engineer

Irvine, CA · On-site

$146.10K - $178.40K/yr

Design Verification Engineer Location: Santa Clara, CA Duration: 06 months (High Possibility of an extension) Senior DV engineer responsible for defining and implementing verification methodology and ...

Description As a Design Verification Engineer, you'll be at the center of our silicon design group's verification efforts, ensuring the quality and reliability of next-generation cellular systems.

Description As a Design Verification Engineer, you'll be at the center of our silicon design group's verification efforts, ensuring the quality and reliability of next-generation cellular systems.

Description As a Design Verification Engineer, you'll be at the center of our silicon design group's verification efforts, ensuring the quality and reliability of next-generation cellular systems.

Design Verification Engineer

Beaverton, OR · On-site

$141.50K - $172.70K/yr

Design Verification Engineers at Apple are responsible for verifying the functionality and performance of Apple's premier SOCs. This is a critical job within Apple's Hardware Technology and we'd love ...

Description As a Design Verification Engineer, you'll be at the center of our silicon design group's verification efforts, ensuring the quality and reliability of next-generation cellular systems.

Design Verification Engineer

San Francisco, CA · On-site

$160.20K - $195.60K/yr

We have an opportunity for an outstandingly hardworking design verification engineer. As a member of our wide-ranging group, you will have the rare and extraordinary opportunity to craft upcoming ...

Design Verification Engineer

Chandler, AZ · On-site

$133.90K - $163.50K/yr

We are seeking an experienced and innovative Design Verification Engineer to join a world-class silicon design verification team. This role partners closely with digital and analog designers, systems ...

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Design Verification Engineer Startup information

See salary details

$105.5K

$149.2K

$167K

How much do design verification engineer startup jobs pay per year?

As of May 30, 2026, the average yearly pay for design verification engineer startup in the United States is $149,150.00, according to ZipRecruiter salary data. Most workers in this role earn between $136,000.00 and $166,000.00 per year, depending on experience, location, and employer.

What are the key skills and qualifications needed to thrive as a Design Verification Engineer at a startup, and why are they important?

To thrive as a Design Verification Engineer at a startup, you need a strong background in digital design, verification methodologies, and a relevant degree in electrical engineering or computer science. Familiarity with tools like SystemVerilog, UVM, simulation environments, and version control systems is typically required, along with experience in scripting languages. Strong problem-solving abilities, adaptability, and effective communication are crucial soft skills, especially in fast-paced startup environments. These skills ensure efficient bug detection, robust product development, and successful collaboration within small, agile teams.

What unique challenges might a Design Verification Engineer face when working at a startup compared to a larger company?

At a startup, Design Verification Engineers often work with smaller teams and less established processes, which means you'll likely take on a broader range of responsibilities—from testbench development to hands-on debugging and even influencing verification methodologies. The fast-paced environment can present challenges such as tighter deadlines, limited resources, and rapidly changing project scopes. However, this setting also allows for closer collaboration with design, software, and product teams, fostering a greater sense of ownership and quicker decision-making. Your contributions are highly visible, and there's significant potential for accelerated career growth as the company scales.

What does a Design Verification Engineer do at a startup?

A Design Verification Engineer at a startup is responsible for ensuring that hardware designs, such as integrated circuits or systems-on-chip, function as intended before they are manufactured. This typically involves developing and running simulations, creating testbenches, writing verification plans, and identifying bugs or mismatches in the design. In a startup environment, Design Verification Engineers often work closely with design, software, and product teams, and may need to wear multiple hats due to limited resources. Their work is crucial in reducing costly errors and speeding up the development cycle, helping the company deliver reliable products to market quickly.

What is the difference between Design Verification Engineer Startup vs Design Verification Engineer Large Corporation?

AspectDesign Verification Engineer StartupDesign Verification Engineer Large Corporation
CredentialsBachelor's or Master's in Electrical Engineering, Computer Engineering, or related fields; certifications like Certified Verification Engineer are commonSame as startup; often similar certifications and educational background
Work EnvironmentAgile, fast-paced, collaborative teams with flexible processesStructured, process-driven, with formal verification methodologies and documentation
Employer & Industry UsageStartups in semiconductor, electronics, or tech sectors; emphasis on innovationLarge tech, semiconductor, or electronics companies with established verification teams
Search & Comparison IntentUnderstanding role differences in startup vs large company

Both roles require similar technical skills and educational backgrounds. The main differences lie in work environment and processes, with startups being more flexible and fast-paced, while large corporations follow formal verification procedures. Candidates should consider their preferred work style when comparing these roles.

More about Design Verification Engineer Startup jobs
What cities are hiring for Design Verification Engineer Startup jobs? Cities with the most Design Verification Engineer Startup job openings:
What states have the most Design Verification Engineer Startup jobs? States with the most job openings for Design Verification Engineer Startup jobs include:
Infographic showing various Design Verification Engineer Startup job openings in the United States as of May 2026, with employment types broken down into 1% As Needed, 29% Full Time, 45% Part Time, 2% Temporary, 22% Contract, and 1% Nights. Highlights an 94% Physical, 2% Hybrid, and 4% Remote job distribution, with an average salary of $149,150 per year, or $71.7 per hour.

Principal Design Verification Engineer

Bolt Graphics

Sunnyvale, CA • On-site

$250K - $280K/yr

Full-time

Medical, Dental, Vision, Retirement

Posted 14 days ago


Job description

Bolt Graphics is a semiconductor startup based in Sunnyvale, CA building the fastest and most efficient graphics processors. We pride ourselves on our first principles approach to solving problems. We are energized by our mission to reduce the barrier of entry for content creation and consumption. Our goal is to enable everyone to easily create, simulate and consume immersive experiences as vividly as they can imagine them.
Our Values
  • Be Fearless: Unmute yourself. Test boundaries and get proven right.
  • Remain Adaptable: Stay comfortable in a continuously changing world. If you're wrong, concede and move on.
  • Educate Your Ego: Selflessly collaborate towards our shared purpose.

About the role:
As a Principal Design Verification Engineer, you will own the verification strategy and execution for complex IPs or full-chip SoC. You will lead a team of verification engineers, define methodologies, drive coverage closure, and ensure high-quality silicon delivery. This is an on-site role and will require presence in the office 5 days a week. No hybrid option is available.
What you'll do:
Leadership & Strategy
  • Define and drive end-to-end verification strategy (block → subsystem → full-chip)
  • Build, mentor, and scale a high-performing DV team
  • Establish verification plans, milestones, and coverage goals
  • Drive alignment across architecture, RTL, and physical design teams

Verification Execution
  • Lead development of UVM-based verification environments
  • Define testbench architecture, stimulus strategy, and reusable components
  • Drive functional, code, and assertion coverage closure
  • Oversee regression infrastructure, debug, and signoff criteria

Advanced Verification & Signoff
  • Drive GLS (Gate-Level Simulation) with SDF annotation and timing-aware debug
  • Manage low-power verification (UPF/CPF) and power-aware simulation
  • Oversee formal verification, linting, CDC/RDC analysis
  • Ensure robust reset, clocking, and cross-domain verification

Cross-Functional Collaboration
  • Work with RTL teams on design-for-verification (DFV) improvements
  • Collaborate with PD teams on timing-related verification issues
  • Support post-silicon bring-up and debug
  • Interface with customers/partners on verification readiness and quality

Required Qualifications:
  • Bachelor's/Master's degree in Electrical Engineering or related field
  • 12-15 years of experience in ASIC/SoC design verification
  • Proven experience leading verification teams and delivering multiple tapeouts
  • Strong expertise in:
    • SystemVerilog and UVM methodology
    • Functional coverage, assertions (SVA), and constrained-random verification
    • Debugging complex SoC-level issues
  • Hands-on experience with industry-standard tools such as:
    • Synopsys VCS / Cadence Xcelium
    • Synopsys Verdi
  • Strong understanding of:
    • Clock/reset domain crossings (CDC/RDC)
    • Low-power verification methodologies
    • Gate-level simulation and SDF annotation
  • Excellent leadership, communication, and problem-solving skills

Preferred Qualifications:
  • Experience in CPU/GPU/AI/Networking SoCs
  • Expertise in GLS debug (X-propagation, SDF issues, timing failures)
  • Familiarity with emulation platforms (e.g., Synopsys ZeBu)
  • Experience with post-silicon validation and bring-up
  • Knowledge of performance verification and system-level validation
  • Strong scripting skills (Python/TCL) for automation and regression scaling

Compensation Range: $250,000-$280,000 per year (California). This range represents the anticipated base pay for this role based in California; the final offer may vary based on qualifications, experience, and location.
Benefits:
  • Medical, Dental, & Vision - 100% covered premiums
  • Equity - Stock Options
  • 401(k) match
  • WFH Hardware

Bolt is committed to building a diverse and inclusive environment in which we recognize and value each other's differences as well as fostering a culture that promotes its core values: Professionalism, Integrity, and Respect. As an equal opportunity employer, all qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, genetic information, national origin, age, disability, or status as a protected veteran.