As a software engineer, you will craft highly efficient software to automate and facilitate chip design and verification processes. What You'll be Doing: * Work as a team to build reliable, scalable ...
As a software engineer, you will craft highly efficient software to automate and facilitate chip design and verification processes. What You'll be Doing: * Work as a team to build reliable, scalable ...
Semiconductor Chip ExpertLocation: Austin, TX, United States We are seeking a highly skilled ... Bachelor's degree in Engineering or related field * Expertise in software and hardware design
Semiconductor Chip ExpertLocation: Austin, TX, United States We are seeking a highly skilled ... Bachelor's degree in Engineering or related field * Expertise in software and hardware design
Principal Physical Design Engineer
Sunnyvale, CA · On-site
$159K - $164K/yr
Principal Physical Design Engineer This role has been designed as 'Hybrid' with an expectation that ... Develop the chip-level clock network and clock stations in collaboration with clock experts.
Principal Physical Design Engineer
Sunnyvale, CA · On-site
$159K - $164K/yr
Principal Physical Design Engineer This role has been designed as 'Hybrid' with an expectation that ... Develop the chip-level clock network and clock stations in collaboration with clock experts.
Principal Physical Design Engineer
Sunnyvale, CA · Hybrid
$159K - $164K/yr
Principal Physical Design Engineer This role has been designed as 'Hybrid' with an expectation that ... Develop the chip-level clock network and clock stations in collaboration with clock experts.
Principal Physical Design Engineer
Sunnyvale, CA · Hybrid
$159K - $164K/yr
Principal Physical Design Engineer This role has been designed as 'Hybrid' with an expectation that ... Develop the chip-level clock network and clock stations in collaboration with clock experts.
Principal Physical Design Engineer
Sunnyvale, CA · Hybrid
$159K - $164K/yr
Principal Physical Design Engineer This role has been designed as 'Hybrid' with an expectation that ... Develop the chip-level clock network and clock stations in collaboration with clock experts.
Principal Physical Design Engineer
Sunnyvale, CA · Hybrid
$159K - $164K/yr
Principal Physical Design Engineer This role has been designed as 'Hybrid' with an expectation that ... Develop the chip-level clock network and clock stations in collaboration with clock experts.
Principal Physical Design Engineer
Sunnyvale, CA · Hybrid
$159K - $164K/yr
Principal Physical Design Engineer This role has been designed as 'Hybrid' with an expectation that ... Develop the chip-level clock network and clock stations in collaboration with clock experts.
Principal Physical Design Engineer
Sunnyvale, CA · Hybrid
$159K - $164K/yr
Principal Physical Design Engineer This role has been designed as 'Hybrid' with an expectation that ... Develop the chip-level clock network and clock stations in collaboration with clock experts.
Digital IC Design Engineer Intern
Fremont, CA · On-site
$35/hr
Team Description: The Brain Interfaces Soc Department delivers chip architecture and silicon ... As a Digital IC Design Engineer Intern, your responsibilities will include: * Micro-architecture ...
Digital IC Design Engineer Intern
Fremont, CA · On-site
$35/hr
Team Description: The Brain Interfaces Soc Department delivers chip architecture and silicon ... As a Digital IC Design Engineer Intern, your responsibilities will include: * Micro-architecture ...
ASIC Physical Design Engineer
New York, NY · On-site
$148K - $153K/yr
We're a small team where everyone works across the chip design process, and we expect our PD engineers to lead with physical design expertise but think like chip designers. You should be comfortable ...
ASIC Physical Design Engineer
New York, NY · On-site
$148K - $153K/yr
We're a small team where everyone works across the chip design process, and we expect our PD engineers to lead with physical design expertise but think like chip designers. You should be comfortable ...
ASIC Physical Design Engineer
$148K - $153K/yr
We're a small team where everyone works across the chip design process, and we expect our PD engineers to lead with physical design expertise but think like chip designers. You should be comfortable ...
ASIC Physical Design Engineer
$148K - $153K/yr
We're a small team where everyone works across the chip design process, and we expect our PD engineers to lead with physical design expertise but think like chip designers. You should be comfortable ...
Team Description: The Brain Interfaces Soc Department delivers chip architecture and silicon ... We are looking for Analog and Mixed-Signal IC Design Engineer Interns who are interested in ...
Team Description: The Brain Interfaces Soc Department delivers chip architecture and silicon ... We are looking for Analog and Mixed-Signal IC Design Engineer Interns who are interested in ...
Founding RTL Design Engineer (San Francisco)
San Francisco, CA · On-site
$180K - $250K/yr
They say chip design never got its GPT moment as there is no training data: 99% of RTL data is closed-source. Software engineers can use Cursor to 10x their productivity, but hardware engineers can't ...
Founding RTL Design Engineer (San Francisco)
San Francisco, CA · On-site
$180K - $250K/yr
They say chip design never got its GPT moment as there is no training data: 99% of RTL data is closed-source. Software engineers can use Cursor to 10x their productivity, but hardware engineers can't ...
Principal Design Engineer
Torrance, CA · On-site
Principal Design Engineer (Principal Analog IC Designer) Reports to: VP of IC Design In Office ... Extensive previous experience in chip design in the power supply field (Analog IC Design, Power ...
Principal Design Engineer
Torrance, CA · On-site
Principal Design Engineer (Principal Analog IC Designer) Reports to: VP of IC Design In Office ... Extensive previous experience in chip design in the power supply field (Analog IC Design, Power ...
FE RTL Infrastructure - CAD Engineer
Austin, TX · On-site
$164K/yr
... chip (SoC). You'll ensure Apple products and services can seamlessly and efficiently handle the ... Description As a Front-End (FE) RTL Infrastructure - CAD Engineer, you will play a major role in ...
FE RTL Infrastructure - CAD Engineer
Austin, TX · On-site
$164K/yr
... chip (SoC). You'll ensure Apple products and services can seamlessly and efficiently handle the ... Description As a Front-End (FE) RTL Infrastructure - CAD Engineer, you will play a major role in ...
FE RTL Infrastructure - CAD Engineer
Beaverton, OR · On-site
$172K/yr
... chip (SoC). You'll ensure Apple products and services can seamlessly and efficiently handle the ... Description As a Front-End (FE) RTL Infrastructure - CAD Engineer, you will play a major role in ...
FE RTL Infrastructure - CAD Engineer
Beaverton, OR · On-site
$172K/yr
... chip (SoC). You'll ensure Apple products and services can seamlessly and efficiently handle the ... Description As a Front-End (FE) RTL Infrastructure - CAD Engineer, you will play a major role in ...
FE RTL Infrastructure - CAD Engineer
Beaverton, OR · On-site
$172K/yr
... chip (SoC). You'll ensure Apple products and services can seamlessly and efficiently handle the ... Description As a Front-End (FE) RTL Infrastructure - CAD Engineer, you will play a major role in ...
FE RTL Infrastructure - CAD Engineer
Beaverton, OR · On-site
$172K/yr
... chip (SoC). You'll ensure Apple products and services can seamlessly and efficiently handle the ... Description As a Front-End (FE) RTL Infrastructure - CAD Engineer, you will play a major role in ...
Principal Design Engineer
Torrance, CA · On-site
$190K - $230K/yr
Principal Design Engineer (Principal Analog IC Designer) Reports to: VP of IC Design In Office ... Extensive previous experience in chip design in the power supply field (Analog IC Design, Power ...
Principal Design Engineer
Torrance, CA · On-site
$190K - $230K/yr
Principal Design Engineer (Principal Analog IC Designer) Reports to: VP of IC Design In Office ... Extensive previous experience in chip design in the power supply field (Analog IC Design, Power ...
CAD Engineer - Signoff Infrastructure
$150K - $277K/yr
We're seeking a CAD Engineer to join our team and develop full-stack web applications that power ... Signoff is the critical final verification stage in chip design where designs are validated against ...
CAD Engineer - Signoff Infrastructure
$150K - $277K/yr
We're seeking a CAD Engineer to join our team and develop full-stack web applications that power ... Signoff is the critical final verification stage in chip design where designs are validated against ...
CAD Engineer - Signoff Infrastructure
$150K - $277K/yr
We're seeking a CAD Engineer to join our team and develop full-stack web applications that power ... Signoff is the critical final verification stage in chip design where designs are validated against ...
CAD Engineer - Signoff Infrastructure
$150K - $277K/yr
We're seeking a CAD Engineer to join our team and develop full-stack web applications that power ... Signoff is the critical final verification stage in chip design where designs are validated against ...
Chip CAD DevOps Engineer, Google Cloud
Sunnyvale, CA · On-site
$62 - $84.75/hr
As a Chip CAD Engineer, you will be working with a highly creative team, innovating new ways to develop hardware, improve upon industry standards, and with the potential to evolve a new paradigm in ...
Chip CAD DevOps Engineer, Google Cloud
Sunnyvale, CA · On-site
$62 - $84.75/hr
As a Chip CAD Engineer, you will be working with a highly creative team, innovating new ways to develop hardware, improve upon industry standards, and with the potential to evolve a new paradigm in ...
ASIC Physical Design Engineer (TSMC / FinFET)
Lafayette, IN · On-site
$130K - $134K/yr
Partner with customers throughout the chip design and manufacturing lifecycle to ensure a smooth ... Basic scripting or programming experience
ASIC Physical Design Engineer (TSMC / FinFET)
Lafayette, IN · On-site
$130K - $134K/yr
Partner with customers throughout the chip design and manufacturing lifecycle to ensure a smooth ... Basic scripting or programming experience
Chip Design Engineer information
See salary details
$40.5K - $51.2K
2% of jobs
$51.2K - $62K
11% of jobs
$67.7K is the 25th percentile. Wages below this are outliers.
$62K - $72.7K
23% of jobs
The median wage is $79.6K / yr.
$72.7K - $83.4K
22% of jobs
$83.4K - $94.1K
17% of jobs
$94.4K is the 75th percentile. Wages above this are outliers.
$94.1K - $104.9K
9% of jobs
$104.9K - $115.6K
6% of jobs
$115.6K - $126.3K
3% of jobs
$126.3K - $137K
3% of jobs
$137K - $147.8K
2% of jobs
$147.8K - $158.5K
1% of jobs
$40.5K
$88.2K
$158.5K
How much do chip design engineer jobs pay per year?
Are chip designers in demand?
What is the salary of microchip design engineer?
What engineer makes $500,000 a year?
What are some typical projects or daily tasks for a Chip Design Engineer?
As a Chip Design Engineer, your daily tasks often include designing and simulating integrated circuits, reviewing schematics, writing and verifying code in hardware description languages, and collaborating closely with layout engineers and verification teams. You may also participate in design reviews, troubleshoot potential issues, and optimize chip performance to meet specific requirements. Working with cross-functional teams, including software engineers and product managers, is common to ensure the chip integrates seamlessly with end products. This role provides opportunities to see your designs progress from concept to final manufacturing, offering valuable hands-on experience at each stage of development.
What are the key skills and qualifications needed to thrive in the Chip Design Engineer position, and why are they important?
To thrive as a Chip Design Engineer, you need a solid background in electrical engineering, digital and analog circuit design, and experience with VLSI principles, usually backed by a relevant degree. Proficiency with industry-standard tools like Cadence, Synopsys, and experience in HDL languages (such as Verilog or VHDL) is highly valued, as are certifications like Certified IC Designer. Strong problem-solving abilities, attention to detail, and effective teamwork and communication skills help set you apart. These competencies are critical for developing reliable, high-performance chips in a collaborative and deadline-driven environment.
What is a Chip Design Engineer job?
A Chip Design Engineer is responsible for designing and developing integrated circuits (ICs) used in electronic devices. They work with hardware description languages (HDLs) like Verilog or VHDL to create digital or analog circuit designs. Their role includes logic design, verification, simulation, and testing to ensure performance and power efficiency. They collaborate with teams across hardware, software, and manufacturing to bring chips from concept to production. Chip Design Engineers are essential in industries like consumer electronics, automotive, and telecommunications.
How much do chip design engineers make?

Job description
NVIDIA has continuously reinvented itself over two decades. Our invention of the GPU in 1999 fueled the growth of the PC gaming market, redefined modern computer graphics, and revolutionized parallel computing. More recently, GPU deep learning ignited modern AI - the next era of computing. NVIDIA is a "learning machine" that constantly evolves by adapting to new challenges that are hard to tackle, that only we can pursue, and that matter to the world. This is our life's work, to amplify human creativity and intelligence. Make the choice to join us today!
Our team is responsible for development and support of infrastructure tools used by design engineers for build and verification of architectural, rtl, and gate level designs. As a software engineer, you will craft highly efficient software to automate and facilitate chip design and verification processes.
What You'll be Doing:
Work as a team to build reliable, scalable and high performance software that are easy to use by hundreds of engineers worldwide.
Develop software tools in C++/Golang to analyze and construct chip designs described in C++, Verilog or domain-specific languages (DSLs).
Research and develop software solutions to allow greater efficiency in architecture, hardware and software teams.
Optimize the daily workflows of the world's top chip modelers and designers.
What We Need to See:
BS (or equivalent experience) and 5+ years of software development experience., MS (or PHD) preferred.
Experienced with C++ or Golang, Unix/Linux.
Solid understanding of algorithms, computer architecture and computer science theory
Experienced with VLSI frontend design and verification
Flexibility/adaptability for working in a global and dynamic environment with different frameworks and requirements
Ways to stand out from the crowd:
Good architecture and RTL design knowledge
Strong expertise in modern C++, compiler, build systems, and database.
Experienced with static and dynamic code analysis tools
You will also be eligible for equity and benefits.
This posting is for an existing vacancy.
NVIDIA uses AI tools in its recruiting processes.
NVIDIA is committed to fostering a diverse work environment and proud to be an equal opportunity employer. As we highly value diversity in our current and future employees, we do not discriminate (including in our hiring and promotion practices) on the basis of race, religion, color, national origin, gender, gender expression, sexual orientation, age, marital status, veteran status, disability status or any other characteristic protected by law.About Nvidia
Sourced by ZipRecruiter
NVIDIA has been transforming computer graphics, PC gaming, and accelerated computing for more than 25 years. It's a unique legacy of innovation that's fueled by great technology--and amazing people. Today, we're tapping into the unlimited potential of AI to define the next era of computing. An era in which our GPU acts as the brains of computers, robots, and self-driving cars that can understand the world. Doing what's never been done before takes vision, innovation, and the world's best talent.
Industry
Computer and electronic product manufacturing
Company size
10,000+ Employees
Headquarters location
Santa Clara, CA, US
Year founded
1993