Agentrys Studio combines AI agents, engineering knowledge, agent-native tools, advanced models, and continuous learning to automate complex chip-design workflows. Our team brings deep experience in ...
Quick apply
Agentrys Studio combines AI agents, engineering knowledge, agent-native tools, advanced models, and continuous learning to automate complex chip-design workflows. Our team brings deep experience in ...
Quick apply
Agentrys Studio combines AI agents, engineering knowledge, agent-native tools, advanced models, and continuous learning to automate complex chip-design workflows. Our team brings deep experience in ...
Team Description: The Brain Interfaces Soc Department delivers chip architecture and silicon ... As a Digital IC Design Engineer Intern, your responsibilities will include: * Micro-architecture ...
Team Description: The Brain Interfaces Soc Department delivers chip architecture and silicon ... As a Digital IC Design Engineer Intern, your responsibilities will include: * Micro-architecture ...
New York, NY ยท On-site
$148K - $153K/yr
We're a small team where everyone works across the chip design process, and we expect our PD engineers to lead with physical design expertise but think like chip designers. You should be comfortable ...
New York, NY ยท On-site
$148K - $153K/yr
We're a small team where everyone works across the chip design process, and we expect our PD engineers to lead with physical design expertise but think like chip designers. You should be comfortable ...
$148K - $153K/yr
We're a small team where everyone works across the chip design process, and we expect our PD engineers to lead with physical design expertise but think like chip designers. You should be comfortable ...
$148K - $153K/yr
We're a small team where everyone works across the chip design process, and we expect our PD engineers to lead with physical design expertise but think like chip designers. You should be comfortable ...
San Jose, CA ยท On-site
$180K - $350K/yr
About ChipAgents ChipAgents is revolutionizing chip design and verification with agentic-AI ... This is an engineering role for someone with exceptional product judgment and strong opinions about ...
New
San Jose, CA ยท On-site
$180K - $350K/yr
About ChipAgents ChipAgents is revolutionizing chip design and verification with agentic-AI ... This is an engineering role for someone with exceptional product judgment and strong opinions about ...
New
$150 - $210/hr
With an experienced engineering leadership team responsible for over 100+ successful chip tape-outs and numerous software solutions for global tech giants, Eximietas Design is committed to innovation ...
New
$150 - $210/hr
With an experienced engineering leadership team responsible for over 100+ successful chip tape-outs and numerous software solutions for global tech giants, Eximietas Design is committed to innovation ...
New
Palo Alto, CA ยท On-site
$100 - $150/hr
We are reinventing chip development and closing the loop between AI and the hardware that fuels it ... We are hiring bestโinโclass engineers and researchers with real depth in RTL and design ...
Palo Alto, CA ยท On-site
$100 - $150/hr
We are reinventing chip development and closing the loop between AI and the hardware that fuels it ... We are hiring bestโinโclass engineers and researchers with real depth in RTL and design ...
Team Description: The Brain Interfaces Soc Department delivers chip architecture and silicon ... We are looking for Analog and Mixed-Signal IC Design Engineer Interns who are interested in ...
Team Description: The Brain Interfaces Soc Department delivers chip architecture and silicon ... We are looking for Analog and Mixed-Signal IC Design Engineer Interns who are interested in ...
San Diego, CA ยท On-site
$150 - $210/hr
With an experienced engineering leadership team responsible for over 100+ successful chip tape-outs and numerous software solutions for global tech giants, Eximietas Design is committed to innovation ...
New
San Diego, CA ยท On-site
$150 - $210/hr
With an experienced engineering leadership team responsible for over 100+ successful chip tape-outs and numerous software solutions for global tech giants, Eximietas Design is committed to innovation ...
New
Torrance, CA ยท On-site
$190K - $230K/yr
Principal Design Engineer (Principal Analog IC Designer) Reports to: VP of IC Design In Office ... Extensive previous experience in chip design in the power supply field (Analog IC Design, Power ...
Torrance, CA ยท On-site
$190K - $230K/yr
Principal Design Engineer (Principal Analog IC Designer) Reports to: VP of IC Design In Office ... Extensive previous experience in chip design in the power supply field (Analog IC Design, Power ...
... Engineer, you'll advance our models' ability to design silicon. Hardware design is difficult and unforgiving - exactly the sort of domain we want Claude to excel at. You'll leverage your chip design ...
... Engineer, you'll advance our models' ability to design silicon. Hardware design is difficult and unforgiving - exactly the sort of domain we want Claude to excel at. You'll leverage your chip design ...
Beaverton, OR ยท On-site
$172K/yr
... chip (SoC). You'll ensure Apple products and services can seamlessly and efficiently handle the ... Description As a Front-End (FE) RTL Infrastructure - CAD Engineer, you will play a major role in ...
Beaverton, OR ยท On-site
$172K/yr
... chip (SoC). You'll ensure Apple products and services can seamlessly and efficiently handle the ... Description As a Front-End (FE) RTL Infrastructure - CAD Engineer, you will play a major role in ...
Beaverton, OR ยท On-site
$175K/yr
... chip (SoC). You'll ensure Apple products and services can seamlessly and efficiently handle the ... Description As a Front-End (FE) RTL Infrastructure - CAD Engineer, you will play a major role in ...
Beaverton, OR ยท On-site
$175K/yr
... chip (SoC). You'll ensure Apple products and services can seamlessly and efficiently handle the ... Description As a Front-End (FE) RTL Infrastructure - CAD Engineer, you will play a major role in ...
Sunnyvale, CA ยท On-site
$196K/yr
Experience in 2.5D/3D package design, including silicon interposer, silicon bridge, and 3D die ... As a Chip Package Signal integrity/Power Integrity (SI/PI) Engineer in the chip implementation team ...
Sunnyvale, CA ยท On-site
$196K/yr
Experience in 2.5D/3D package design, including silicon interposer, silicon bridge, and 3D die ... As a Chip Package Signal integrity/Power Integrity (SI/PI) Engineer in the chip implementation team ...
Principal Design Engineer (Principal Analog IC Designer) Reports to: VP of IC Design In Office ... Extensive previous experience in chip design in the power supply field (Analog IC Design, Power ...
Principal Design Engineer (Principal Analog IC Designer) Reports to: VP of IC Design In Office ... Extensive previous experience in chip design in the power supply field (Analog IC Design, Power ...
Beaverton, OR ยท On-site
$172K/yr
... chip (SoC). You'll ensure Apple products and services can seamlessly and efficiently handle the ... Description As a Front-End (FE) RTL Infrastructure - CAD Engineer, you will play a major role in ...
Beaverton, OR ยท On-site
$172K/yr
... chip (SoC). You'll ensure Apple products and services can seamlessly and efficiently handle the ... Description As a Front-End (FE) RTL Infrastructure - CAD Engineer, you will play a major role in ...
$150K - $277K/yr
We're seeking a CAD Engineer to join our team and develop full-stack web applications that power ... Signoff is the critical final verification stage in chip design where designs are validated against ...
$150K - $277K/yr
We're seeking a CAD Engineer to join our team and develop full-stack web applications that power ... Signoff is the critical final verification stage in chip design where designs are validated against ...
$150K - $277K/yr
We're seeking a CAD Engineer to join our team and develop full-stack web applications that power ... Signoff is the critical final verification stage in chip design where designs are validated against ...
$150K - $277K/yr
We're seeking a CAD Engineer to join our team and develop full-stack web applications that power ... Signoff is the critical final verification stage in chip design where designs are validated against ...
Lafayette, IN ยท On-site
$130K - $134K/yr
Partner with customers throughout the chip design and manufacturing lifecycle to ensure a smooth ... Basic scripting or programming experience
Lafayette, IN ยท On-site
$130K - $134K/yr
Partner with customers throughout the chip design and manufacturing lifecycle to ensure a smooth ... Basic scripting or programming experience
NVIDIA is seeking ASIC Design Engineers with experience in agentic AI to help design and implement ... As part of NVIDIA's "AI for chip design" team, you will have the opportunity to tap into the ...
NVIDIA is seeking ASIC Design Engineers with experience in agentic AI to help design and implement ... As part of NVIDIA's "AI for chip design" team, you will have the opportunity to tap into the ...
$40.5K - $51.2K
2% of jobs
$51.2K - $62K
11% of jobs
$67.7K is the 25th percentile. Wages below this are outliers.
$62K - $72.7K
23% of jobs
The median wage is $79.6K / yr.
$72.7K - $83.4K
22% of jobs
$83.4K - $94.1K
17% of jobs
$94.4K is the 75th percentile. Wages above this are outliers.
$94.1K - $104.9K
9% of jobs
$104.9K - $115.6K
6% of jobs
$115.6K - $126.3K
3% of jobs
$126.3K - $137K
3% of jobs
$137K - $147.8K
2% of jobs
$147.8K - $158.5K
1% of jobs
$40.5K
$88.2K
$158.5K
As a Chip Design Engineer, your daily tasks often include designing and simulating integrated circuits, reviewing schematics, writing and verifying code in hardware description languages, and collaborating closely with layout engineers and verification teams. You may also participate in design reviews, troubleshoot potential issues, and optimize chip performance to meet specific requirements. Working with cross-functional teams, including software engineers and product managers, is common to ensure the chip integrates seamlessly with end products. This role provides opportunities to see your designs progress from concept to final manufacturing, offering valuable hands-on experience at each stage of development.
To thrive as a Chip Design Engineer, you need a solid background in electrical engineering, digital and analog circuit design, and experience with VLSI principles, usually backed by a relevant degree. Proficiency with industry-standard tools like Cadence, Synopsys, and experience in HDL languages (such as Verilog or VHDL) is highly valued, as are certifications like Certified IC Designer. Strong problem-solving abilities, attention to detail, and effective teamwork and communication skills help set you apart. These competencies are critical for developing reliable, high-performance chips in a collaborative and deadline-driven environment.
A Chip Design Engineer is responsible for designing and developing integrated circuits (ICs) used in electronic devices. They work with hardware description languages (HDLs) like Verilog or VHDL to create digital or analog circuit designs. Their role includes logic design, verification, simulation, and testing to ensure performance and power efficiency. They collaborate with teams across hardware, software, and manufacturing to bring chips from concept to production. Chip Design Engineers are essential in industries like consumer electronics, automotive, and telecommunications.
Cities with the most Chip Design Engineer job openings:
The top employers for Chip Design Engineer jobs are:
States with the most job openings for Chip Design Engineer jobs include:
The top searched job categories for Chip Design Engineer jobs are:

Full-time
Posted 19 days ago
Full-time · On-site · San Jose, CA · Austin, TX or Taiwan
About Agentrys
Agentrys is building the next generation of design automation for the semiconductor industry.
Our mission is to enable every engineering organization to build its own self-improving agentic design workforce. Agentrys Studio combines AI agents, engineering knowledge, agent-native tools, advanced models, and continuous learning to automate complex chip-design workflows.
Our team brings deep experience in artificial intelligence, electronic design automation, semiconductor design, GPU-accelerated computing, and production software systems. We work closely with leading semiconductor companies to turn advanced research into technology that improves engineering productivity, design quality, and time to market.
The Role
We are looking for an exceptional Research Engineer to develop new technologies at the intersection of artificial intelligence, agentic systems, GPU-accelerated computing, and Electronic Design Automation.
You will identify important research problems, develop novel algorithms and agent-native tools, build working prototypes, and help deploy them in real semiconductor design environments. Your work may span AI agents, large language models, reinforcement learning, optimization, GPU-accelerated algorithms, verification, analog design, and other areas of chip design automation.
This role is ideal for someone who combines strong research ability with exceptional implementation skills and wants to see their ideas used in production—not remain only in papers or prototypes.
What You'll Do
Develop new AI and agentic methods for semiconductor design and verification.
Build novel agent-native tools and algorithms designed specifically for autonomous engineering workflows, rather than adapting interfaces built primarily for human users.
Develop GPU-accelerated algorithms for computationally intensive design, analysis, search, simulation, and optimization problems.
Create tools that expose design state, constraints, actions, feedback, and optimization objectives in forms that agents can reason over and use effectively.
Build agents that can understand engineering objectives, use EDA tools, execute multi-step workflows, analyze results, recover from failures, and improve over time.
Research and implement techniques involving large language models, reinforcement learning, parallel algorithms, search, optimization, program synthesis, and machine learning for engineering systems.
Develop solutions for workflows such as functional verification, analog and custom design, RTL development, synthesis, timing analysis, and physical design.
Design rigorous evaluation methods for engineering agents, including problems where design data is private, sparse, or customer-specific.
Translate promising research ideas into reliable, scalable product capabilities.
Integrate AI systems with simulators, formal tools, design databases, commercial EDA tools, GPU computing platforms, and customer engineering infrastructure.
Work directly with semiconductor engineers to understand complex workflows and identify high-impact automation opportunities.
Collaborate with research, product, platform, and solutions teams across San Jose, Austin, and Taiwan.
Contribute to patents, publications, technical presentations, and the broader development of Agentic Design Automation.
What We're Looking For
PhD or master's degree in Computer Science, Electrical Engineering, Computer Engineering, or a related field, or equivalent practical experience.
Strong programming skills in Python and proficiency in at least one systems language such as C++ or Rust.
Experience with machine learning frameworks such as PyTorch or JAX.
Demonstrated research or engineering experience in one or more of the following:
Electronic Design Automation
Semiconductor design or verification
Agentic AI or large language models
GPU-accelerated or parallel algorithms
Reinforcement learning
Combinatorial optimization
Program synthesis or code generation
Formal methods
Machine learning for engineering or scientific applications
Ability to take an ambiguous technical problem from initial formulation through experimentation, implementation, and evaluation.
Strong analytical, software engineering, optimization, and debugging skills.
High ownership, intellectual curiosity, and willingness to work across research and product boundaries.
Clear written and verbal communication skills.
Particularly Valuable Experience
Publications in leading EDA, AI, machine learning, systems, high-performance computing, or computer architecture venues.
Experience developing new EDA algorithms, optimization engines, design representations, or domain-specific tools.
Experience developing GPU-accelerated algorithms using CUDA, Triton, or related parallel-computing technologies.
Experience profiling and optimizing computational workloads across CPUs and GPUs.
Experience designing tools or environments for use by autonomous agents.
Experience with simulation, verification, synthesis, timing analysis, physical design, analog design, or layout.
Experience building agents that interact with tools, codebases, databases, or external environments.
Experience with LLM training, post-training, fine-tuning, retrieval, tool use, or evaluation.
Familiarity with Verilog, SystemVerilog, assertions, SPICE, TCL, or semiconductor design flows.
Experience with commercial EDA tools or production chip-design environments.
Experience deploying AI systems in enterprise or security-sensitive environments.
A strong record of implementation through research systems, open-source projects, production software, or technical competitions.
Why Agentrys
At Agentrys, you will have the opportunity to:
Help define a new category of semiconductor design technology.
Invent the agent-native algorithms and tools that will form the foundation of future automated design workflows.
Develop GPU-accelerated algorithms that make previously impractical design and optimization workflows possible.
Build AI systems that perform complex, consequential engineering work—not just generate recommendations.
Work with real semiconductor workflows, tools, and private engineering knowledge.
See your research deployed directly with leading chip-design organizations.
Work in a small, highly technical team where individual contributions can shape the product and company.
Collaborate with colleagues across San Jose, Austin, and Taiwan.
Change how chips are designed, rather than focus on only one design or one point tool.
Sourced by ZipRecruiter
Recruiting and staffing services
51 - 200 Employees
Bellevue, WA, US
2014