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Asic Verification Manager Jobs (NOW HIRING)

K2 Space

Principal ASIC Design Verification Engineer

OR · On-site +1

$190K - $285K/yr

  • Medical

  • Dental

  • Vision

  • Life

  • PTO

Manage regression testing, simulation farms, and CI pipelines to ensure high test throughput and ... in ASIC/SoC verification. * Solid understanding of SystemVerilog, digital logic, RTL design, DFT ...

K2 Space

Principal ASIC Design Verification Engineer

Seattle, WA · On-site

$190K - $285K/yr

  • Medical

  • Dental

  • Vision

  • Life

  • PTO

Manage regression testing, simulation farms, and CI pipelines to ensure high test throughput and ... in ASIC/SoC verification. * Solid understanding of SystemVerilog, digital logic, RTL design, DFT ...

Broadcom

Verification Engineer

San Jose, CA · On-site

$159K/yr

  • Medical

  • Dental

  • Vision

  • Retirement

  • PTO

You will be joining Broadcom's custom silicon division, working on IPs for ASIC products such as ... and managing automated verification environment would be a plus Excellent communication skills ...

Broadcom

Verification Engineer

Allentown, PA · On-site

$134K/yr

  • Medical

  • Dental

  • Vision

  • Retirement

  • PTO

You will be joining Broadcom's custom silicon division, working on IPs for ASIC products such as ... and managing automated verification environment would be a plus Excellent communication skills ...

K2 Space

Principal ASIC Design Verification Engineer

Seattle, WA · On-site

$190K - $285K/yr

  • Medical

  • Dental

  • Vision

  • Life

  • PTO

Manage regression testing, simulation farms, and CI pipelines to ensure high test throughput and ... in ASIC/SoC verification. * Solid understanding of SystemVerilog, digital logic, RTL design, DFT ...

K2 Space

Principal ASIC Design Verification Engineer

$190K - $285K/yr

  • Medical

  • Dental

  • Vision

  • Life

  • PTO

Manage regression testing, simulation farms, and CI pipelines to ensure high test throughput and ... in ASIC/SoC verification. * Solid understanding of SystemVerilog, digital logic, RTL design, DFT ...

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$144.4K

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How much do asic verification manager jobs pay per year?

As of Aug 16, 2026, the average yearly pay for asic verification manager in the United States is $144,372.00, according to ZipRecruiter salary data. Most workers in this role earn between $95,000.00 and $190,000.00 per year, depending on experience, location, and employer.

What are the key skills and qualifications needed to thrive in the Asic Verification Manager position, and why are they important?

To thrive as an ASIC Verification Manager, you need a deep understanding of digital design and verification methodologies, experience with hardware description languages (HDLs) such as Verilog or VHDL, and a degree in electrical engineering or a related field. Familiarity with verification tools like UVM, SystemVerilog, simulation environments, and code coverage analysis is typically required, along with knowledge of industry standards. Strong leadership, project management, effective communication, and team-building abilities help set top candidates apart. These skills and qualities are critical to ensuring thorough verification cycles, timely project delivery, and successful cross-functional team collaboration in complex semiconductor development projects.

What are some of the primary challenges faced by Asic Verification Managers in their daily work?

ASIC Verification Managers often navigate the complexities of verifying highly integrated, feature-rich designs under tight development timelines. They manage large teams of engineers, coordinate cross-functional communication with design, physical implementation, and firmware groups, and are responsible for developing and executing comprehensive verification plans. Balancing resource allocation, ensuring thorough test coverage, and adapting to evolving project requirements are common challenges. Success in this role often depends on strong organizational skills, attention to technical detail, and the ability to anticipate and resolve verification bottlenecks promptly.

What does an Asic Verification Manager do?

An ASIC Verification Manager leads a team responsible for verifying the functionality and performance of ASIC designs before production. They develop verification strategies, oversee testbench creation, and ensure compliance with design specifications. Their role includes managing project timelines, collaborating with design and software teams, and improving verification methodologies. Strong leadership, technical expertise in verification tools, and experience in UVM and SystemVerilog are essential for success in this role.

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Asic Verification Manager jobs near you
Infographic showing various Asic Verification Manager job openings in the United States as of August 2026, with employment types broken down into 100% Full Time. Highlights an 100% In-person job distribution, with an average salary of $144,372 per year, or $69.4 per hour.

Principal ASIC Design Verification Engineer

K2 Space

OR • On-site, Remote

$190K - $285K/yr

Full-time

Medical, Dental, Vision, Life, PTO

Re-posted 21 days ago

Job description

The Role 

We are seeking a Principal ASIC Design Verification Engineer whose role will be to verify the functionality, performance, and robustness of our custom silicon designs. You will help define the verification approach, contribute to methodology, and work closely with architecture, RTL design, DFT, firmware, physical design, and silicon validation engineers. This is a hands-on role with high ownership, deep technical engagement, and the opportunity to shape first-generation silicon. 

Responsibilities 

  • Develop and execute verification plans for block-level, subsystem-level, and full-chip environments.
  • Build SystemVerilog/UVM test benches, including agents, monitors, scoreboards, checkers, and coverage models.
  • Write SystemVerilog Assertions (SVA) and integrate formal verification where appropriate.
  • Drive constrained-random and directed testing strategies to validate functionality, corner cases, and stress scenarios.
  • Run simulations, triage failures, drive root-cause analysis, and collaborate with RTL designers to resolve issues.
  • Implement and maintain functional coverage, code coverage, assertion coverage, and ensure coverage closure for sign-off.
  • Manage regression testing, simulation farms, and CI pipelines to ensure high test throughput and fast debug iterations.
  • Participate in design reviews, microarchitecture discussions, and influence design-for-verification (DFV) best practices.
  • Work closely with architecture, RTL design, DFT, firmware, physical design, and silicon validation engineers to ensure end-to-end coverage and test.
  • Support silicon bring-up and post-silicon validation through test reuse, diagnostics, and debug analysis.
  • Participate in ASIC team interviews.
  • Drive advancement of DV methodologies and improvements.
  • Manage external IP providers and verification partners when needed.
  • Take lead on large and/or complex systems. 

Qualifications 

  • B.S. or M.S. in Electrical Engineering, Computer Engineering, or related field.
  • 10+ years of experience in ASIC/SoC verification.
  • Solid understanding of SystemVerilog, digital logic, RTL design, DFT, and hardware design and verification flows.
  • Proficiency with several simulation (VCS, Xcelium, Questa), waveform debug (Verdi, SimVision), coverage tools, and scripting languages (ex: Python, Perl, TCL).
  • Experience with test planning, UVM-based testbench development, constrained-random testing, functional coverage, and SystemVerilog assertions.
  • Experience with regression management, coverage analysis, revision control (ex: Git), CI/CD automation, and gate-level simulation.
  • Experience with developing and integrating reference models.
  • Experience with embedded processor-based designs and firmware/bare metal coding (ex: C, C++).
  • Understanding of many industry-standard interfaces (ex: APB/AHB/AXI).
  • Involvement in post-silicon validation planning and execution. 

Nice to Have

  • Experience with low power verification.
  • Experience with analog behavioral models.
  • Familiarity with physical design flows.
  • Experience working in cross-functional, geographically distributed teams.
  • Experience in space, telecom, or RF/digital mixed systems is a plus. 

Compensation and Benefits:

  • Base salary range for this role is $190,000 - $285,000 + equity in the company
  • Salary will be based on several factors including, but not limited to: knowledge and skills, education, and experience level
  • Comprehensive benefits package including paid time off, medical/dental/vision/ coverage, life insurance, paid parental leave, and many other perks
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About K2 Space

Sourced by ZipRecruiter

Industry

Guided missile and space vehicle manufacturing

Company size

11 - 50 Employees

Headquarters location

Los Angeles, CA, US

Year founded

2022

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