Meta's Infrastructure Silicon team is seeking a Staff ASIC Design Verification Engineer to lead verification strategy and execution for custom silicon p.
Meta's Infrastructure Silicon team is seeking a Staff ASIC Design Verification Engineer to lead verification strategy and execution for custom silicon p.
Lead, mentor, and manage a team of verification engineers to meet project milestones and deliverables. * Define and execute verification strategies and plans for complex digital blocks and systems.
Lead, mentor, and manage a team of verification engineers to meet project milestones and deliverables. * Define and execute verification strategies and plans for complex digital blocks and systems.
Verification CAD Lead
Austin, TX · On-site
... manage engineering loads across multiple teams. What You'll Own: • Lead the development and implementation of advanced verification methodologies for ASIC IP and SoC projects. • Oversee the ...
Verification CAD Lead
Austin, TX · On-site
... manage engineering loads across multiple teams. What You'll Own: • Lead the development and implementation of advanced verification methodologies for ASIC IP and SoC projects. • Oversee the ...
... ASIC implementations in Verilog/SystemVerilog • Run formal verification of complex blocks to ... manage stress and work safely and respectfully with others, exhibit trustworthiness and ...
... ASIC implementations in Verilog/SystemVerilog • Run formal verification of complex blocks to ... manage stress and work safely and respectfully with others, exhibit trustworthiness and ...
ASIC Engineer, Design Verification
Austin, TX · On-site +1
$114K/yr
Meta is hiring an ASIC Design Verification Engineer within the Infrastructure Silicon organization ... management * Participate in design reviews and verification planning discussions to identify ...
ASIC Engineer, Design Verification
Austin, TX · On-site +1
$114K/yr
Meta is hiring an ASIC Design Verification Engineer within the Infrastructure Silicon organization ... management * Participate in design reviews and verification planning discussions to identify ...
Design Verification (DV) Engineer
Austin, TX · On-site
$134K - $164K/yr
FPGA and ASIC verification is part of an innovative, growing team at HRT which is integral to the ... Managing test suites and continuous integration infrastructure * Developing and improving open ...
Design Verification (DV) Engineer
Austin, TX · On-site
$134K - $164K/yr
FPGA and ASIC verification is part of an innovative, growing team at HRT which is integral to the ... Managing test suites and continuous integration infrastructure * Developing and improving open ...
ASIC Engineer, Power Management Design Verification
Austin, TX · On-site +1
$178K/yr
ASIC Engineer, Power Management Design Verification Responsibilities: * Define and implement IP/SoC verification plans, build verification test benches to enable IP/sub-system/SoC level verification
ASIC Engineer, Power Management Design Verification
Austin, TX · On-site +1
$178K/yr
ASIC Engineer, Power Management Design Verification Responsibilities: * Define and implement IP/SoC verification plans, build verification test benches to enable IP/sub-system/SoC level verification
... verification, FPGA prototyping, Emulation, Physical design, BROM, FW, substrate and package design ... management teams to develop ASIC/SOCs solutions that will go into Satellites and Ground equipment ...
... verification, FPGA prototyping, Emulation, Physical design, BROM, FW, substrate and package design ... management teams to develop ASIC/SOCs solutions that will go into Satellites and Ground equipment ...
... verification, FPGA prototyping, Emulation, Physical design, BROM, FW, substrate and package design ... management teams to develop ASIC/SOCs solutions that will go into Satellites and Ground equipment ...
... verification, FPGA prototyping, Emulation, Physical design, BROM, FW, substrate and package design ... management teams to develop ASIC/SOCs solutions that will go into Satellites and Ground equipment ...
This role supports advanced power management products for demanding compute, AI, datacenter, and infrastructure applications. Renesas is seeking an experienced Mixed Signal Verification Architect to ...
This role supports advanced power management products for demanding compute, AI, datacenter, and infrastructure applications. Renesas is seeking an experienced Mixed Signal Verification Architect to ...
... verification, FPGA prototyping, Emulation, Physical design, BROM, FW, substrate and package design ... management teams to develop ASIC/SOCs solutions that will go into Satellites and Ground equipment ...
... verification, FPGA prototyping, Emulation, Physical design, BROM, FW, substrate and package design ... management teams to develop ASIC/SOCs solutions that will go into Satellites and Ground equipment ...
Principal PCIe Subsystem Verification Engineer
Austin, TX · Hybrid
$249K - $338K/yr
As a creative verification engineer with a knowledge of Sub-System integration verification, IO ... Knowledge of System Memory Management Unit and Generic Interrupt Controller Integration with PCIe.
Principal PCIe Subsystem Verification Engineer
Austin, TX · Hybrid
$249K - $338K/yr
As a creative verification engineer with a knowledge of Sub-System integration verification, IO ... Knowledge of System Memory Management Unit and Generic Interrupt Controller Integration with PCIe.
Design Verification Engineer
Plano, TX · On-site
$130K - $158K/yr
and other details - We are seeking an ASIC Design Verification Engineer whose role will be to ... Manage regression testing, simulation farms, and CI pipelines to ensure high test throughput and ...
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Design Verification Engineer
Plano, TX · On-site
$130K - $158K/yr
and other details - We are seeking an ASIC Design Verification Engineer whose role will be to ... Manage regression testing, simulation farms, and CI pipelines to ensure high test throughput and ...
Principal PCIe Subsystem Verification Engineer
Austin, TX · On-site
$249K - $338K/yr
Knowledge of System Memory Management Unit and Generic Interrupt Controller Integration with PCIe ... Good knowledge of verification strategies like test plan creation, tasks tracking, coverage and ...
Principal PCIe Subsystem Verification Engineer
Austin, TX · On-site
$249K - $338K/yr
Knowledge of System Memory Management Unit and Generic Interrupt Controller Integration with PCIe ... Good knowledge of verification strategies like test plan creation, tasks tracking, coverage and ...
Senior Principal Firmware Engineering Lead
Mckinney, TX · On-site
$110K - $146K/yr
FPGA/ASIC design (VHDL and/or Verilog coding) or FPGA/ASIC verification (System Verilog coding ... Experience managing technical, cost, and schedule risks and opportunities. * Experience with ...
Senior Principal Firmware Engineering Lead
Mckinney, TX · On-site
$110K - $146K/yr
FPGA/ASIC design (VHDL and/or Verilog coding) or FPGA/ASIC verification (System Verilog coding ... Experience managing technical, cost, and schedule risks and opportunities. * Experience with ...
Senior Principal Firmware Engineering Lead with Security Clearance
Mckinney, TX · On-site
$110K - $146K/yr
FPGA/ASIC design (VHDL and/or Verilog coding) or FPGA/ASIC verification (System Verilog coding ... Experience managing technical, cost, and schedule risks and opportunities. * Experience with ...
Senior Principal Firmware Engineering Lead with Security Clearance
Mckinney, TX · On-site
$110K - $146K/yr
FPGA/ASIC design (VHDL and/or Verilog coding) or FPGA/ASIC verification (System Verilog coding ... Experience managing technical, cost, and schedule risks and opportunities. * Experience with ...
Senior Principal Firmware Engineering Lead
$110K - $146K/yr
FPGA/ASIC design (VHDL and/or Verilog coding) or FPGA/ASIC verification (System Verilog coding ... Experience managing technical, cost, and schedule risks and opportunities. * Experience with ...
Senior Principal Firmware Engineering Lead
$110K - $146K/yr
FPGA/ASIC design (VHDL and/or Verilog coding) or FPGA/ASIC verification (System Verilog coding ... Experience managing technical, cost, and schedule risks and opportunities. * Experience with ...
Senior Principal Firmware Engineering Lead
Mckinney, TX · On-site
$110K - $146K/yr
FPGA/ASIC design (VHDL and/or Verilog coding) or FPGA/ASIC verification (System Verilog coding ... Experience managing technical, cost, and schedule risks and opportunities. * Experience with ...
Senior Principal Firmware Engineering Lead
Mckinney, TX · On-site
$110K - $146K/yr
FPGA/ASIC design (VHDL and/or Verilog coding) or FPGA/ASIC verification (System Verilog coding ... Experience managing technical, cost, and schedule risks and opportunities. * Experience with ...
Principal FPGA Engineer
Mckinney, TX · On-site
$129K - $157K/yr
Identify and manage project risks and opportunities. * Create complete documentation including ... FPGA/ASIC design (VHDL and/or Verilog coding) or FPGA/ASIC verification (System Verilog coding)
Principal FPGA Engineer
Mckinney, TX · On-site
$129K - $157K/yr
Identify and manage project risks and opportunities. * Create complete documentation including ... FPGA/ASIC design (VHDL and/or Verilog coding) or FPGA/ASIC verification (System Verilog coding)
Silicon Design Verification Engineer
Austin, TX · Hybrid
$134K - $164K/yr
Strong understanding of different phases of ASIC and/or full custom chip development is required ... Familiarity with verification management tools as well as understanding of database management ...
Silicon Design Verification Engineer
Austin, TX · Hybrid
$134K - $164K/yr
Strong understanding of different phases of ASIC and/or full custom chip development is required ... Familiarity with verification management tools as well as understanding of database management ...
Asic Verification Manager information
What are the key skills and qualifications needed to thrive in the Asic Verification Manager position, and why are they important?
To thrive as an ASIC Verification Manager, you need a deep understanding of digital design and verification methodologies, experience with hardware description languages (HDLs) such as Verilog or VHDL, and a degree in electrical engineering or a related field. Familiarity with verification tools like UVM, SystemVerilog, simulation environments, and code coverage analysis is typically required, along with knowledge of industry standards. Strong leadership, project management, effective communication, and team-building abilities help set top candidates apart. These skills and qualities are critical to ensuring thorough verification cycles, timely project delivery, and successful cross-functional team collaboration in complex semiconductor development projects.
What are some of the primary challenges faced by Asic Verification Managers in their daily work?
ASIC Verification Managers often navigate the complexities of verifying highly integrated, feature-rich designs under tight development timelines. They manage large teams of engineers, coordinate cross-functional communication with design, physical implementation, and firmware groups, and are responsible for developing and executing comprehensive verification plans. Balancing resource allocation, ensuring thorough test coverage, and adapting to evolving project requirements are common challenges. Success in this role often depends on strong organizational skills, attention to technical detail, and the ability to anticipate and resolve verification bottlenecks promptly.
What does an Asic Verification Manager do?
An ASIC Verification Manager leads a team responsible for verifying the functionality and performance of ASIC designs before production. They develop verification strategies, oversee testbench creation, and ensure compliance with design specifications. Their role includes managing project timelines, collaborating with design and software teams, and improving verification methodologies. Strong leadership, technical expertise in verification tools, and experience in UVM and SystemVerilog are essential for success in this role.

Meta rating
7.8
Based on 45 frontline employees who took The Breakroom Quiz
135th of 242 rated software companies
Job description
Meta's Infrastructure Silicon team is seeking a Staff ASIC Design Verification Engineer to lead verification strategy and execution for custom silicon p...
About Meta
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Industry
Internet and it, media and telecom and software development
Company size
10,000+ Employees
Headquarters location
Menlo Park, CA, US