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Asic Verification Manager Jobs in Oregon (NOW HIRING)

Rambus

PE Logic Design

Hillsboro, OR · Hybrid

$127K - $236K/yr

Solid communication and project management skills * 10+ years of logic design experience (ASIC/FPGA ... ASIC synthesis, timing constraint, CDC/RDC experience * UVM Verification experience * Memory (HBM ...

Rambus

Principal Logic Design Engineer

Hillsboro, OR · Hybrid

$127K - $287K/yr

Solid communication and project management skills * 10+ years of logic design experience (ASIC/FPGA ... ASIC synthesis, timing constraint, CDC/RDC experience * UVM Verification experience * Memory (HBM ...

Rambus

Principal Logic Design Engineer

Hillsboro, OR · Hybrid

$127K - $287K/yr

Solid communication and project management skills * 10+ years of logic design experience (ASIC/FPGA ... ASIC synthesis, timing constraint, CDC/RDC experience * UVM Verification experience * Memory (HBM ...

Apple

Timing Design Engineer

Beaverton, OR · On-site

Description As an ASIC STA Engineer, you will have responsibilities spanning all aspects of SoC ... You will also come up with ideas and plans to verify your own timing constraints. You will innovate ...

Apple

Timing Design Engineer

Beaverton, OR · On-site

Description As an ASIC STA Engineer, you will have responsibilities spanning all aspects of SoC ... You will also come up with ideas and plans to verify your own timing constraints. You will innovate ...

Apple

Timing Design Engineer

Beaverton, OR · On-site

Description As an ASIC STA Engineer, you will have responsibilities spanning all aspects of SoC ... You will also come up with ideas and plans to verify your own timing constraints. You will innovate ...

Apple

Timing Design Engineer

Beaverton, OR · On-site

Description As an ASIC STA Engineer, you will have responsibilities spanning all aspects of SoC ... You will also come up with ideas and plans to verify your own timing constraints. You will innovate ...

Rambus.com

Principal Logic Design Engineer

Hillsboro, OR · On-site

$127.40 - $236.60/hr

Solid communication and project management skills * 10+ years of logic design experience (ASIC/FPGA ... ASIC synthesis, timing constraint, CDC/RDC experience * UVM Verification experience * Memory (HBM ...

Rambus

Principal Logic Design Engineer

Hillsboro, OR · On-site

$127K - $287K/yr

Solid communication and project management skills * 10+ years of logic design experience (ASIC/FPGA ... ASIC synthesis, timing constraint, CDC/RDC experience * UVM Verification experience * Memory (HBM ...

Rambus

PE Logic Design

Hillsboro, OR · On-site

$127K - $236K/yr

Solid communication and project management skills * 10+ years of logic design experience (ASIC/FPGA ... ASIC synthesis, timing constraint, CDC/RDC experience * UVM Verification experience * Memory (HBM ...

Rambus

PE Logic Design

Hillsboro, OR · Hybrid

$127K - $236K/yr

Solid communication and project management skills * 10+ years of logic design experience (ASIC/FPGA ... ASIC synthesis, timing constraint, CDC/RDC experience * UVM Verification experience * Memory (HBM ...

Rambus

Principal Logic Design Engineer

Hillsboro, OR · Hybrid

$127K - $287K/yr

Solid communication and project management skills * 10+ years of logic design experience (ASIC/FPGA ... ASIC synthesis, timing constraint, CDC/RDC experience * UVM Verification experience * Memory (HBM ...

Rambus

Principal Logic Design Engineer

Hillsboro, OR · Hybrid

$127K - $287K/yr

Solid communication and project management skills * 10+ years of logic design experience (ASIC/FPGA ... ASIC synthesis, timing constraint, CDC/RDC experience * UVM Verification experience * Memory (HBM ...

Intel

Director, Engineering

Hillsboro, OR · On-site

... and ASIC/Foundry products.Partner closely with Architecture, Circuit Design, RTL Design, Verification, Package, Product Engineering, and Technology Development teams.Manage schedule, resource ...

Rambus

Hardware Design Engineer

Hillsboro, OR · Hybrid

$106K - $198K/yr

Solid communication and project management skills * 5+ years of logic design experience * BSEE Definite Plus: * ASIC synthesis, timing constraint, CDC/RDC experience * Verification experience

Rambus

Hardware Design Engineer

Hillsboro, OR · Hybrid

$106K - $198K/yr

Solid communication and project management skills * 5+ years of logic design experience * BSEE Definite Plus: * ASIC synthesis, timing constraint, CDC/RDC experience * Verification experience

Rambus

Hardware Design Engineer

Hillsboro, OR · On-site

$106K - $198K/yr

Solid communication and project management skills * 5+ years of logic design experience * BSEE Definite Plus: * ASIC synthesis, timing constraint, CDC/RDC experience * Verification experience

Intel

EDA Tools SW Engineer

Hillsboro, OR · Hybrid

$173K - $330K/yr

... ASIC tools/flows and Physical verification/runsets, Tape-in Verification and IP sign off for test ... Technical management or lead experience mentoring or leading medium sized teams. * Experience with ...

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Showing results 21-40

All JobsAsic Verification JobsAsic Verification Manager JobsAsic Verification Manager Jobs in Oregon

Asic Verification Manager information

See Oregon salary details

$26.9K

$144K

$218.9K

How much do asic verification manager jobs pay per year?

As of Sep 7, 2026, the average yearly pay for asic verification manager in Oregon is $143,998.00, according to ZipRecruiter salary data. Most workers in this role earn between $94,753.00 and $189,507.00 per year, depending on experience, location, and employer.

What does an Asic Verification Manager do?

An ASIC Verification Manager leads a team responsible for verifying the functionality and performance of ASIC designs before production. They develop verification strategies, oversee testbench creation, and ensure compliance with design specifications. Their role includes managing project timelines, collaborating with design and software teams, and improving verification methodologies. Strong leadership, technical expertise in verification tools, and experience in UVM and SystemVerilog are essential for success in this role.

What are some of the primary challenges faced by Asic Verification Managers in their daily work?

ASIC Verification Managers often navigate the complexities of verifying highly integrated, feature-rich designs under tight development timelines. They manage large teams of engineers, coordinate cross-functional communication with design, physical implementation, and firmware groups, and are responsible for developing and executing comprehensive verification plans. Balancing resource allocation, ensuring thorough test coverage, and adapting to evolving project requirements are common challenges. Success in this role often depends on strong organizational skills, attention to technical detail, and the ability to anticipate and resolve verification bottlenecks promptly.

What are the key skills and qualifications needed to thrive in the Asic Verification Manager position, and why are they important?

To thrive as an ASIC Verification Manager, you need a deep understanding of digital design and verification methodologies, experience with hardware description languages (HDLs) such as Verilog or VHDL, and a degree in electrical engineering or a related field. Familiarity with verification tools like UVM, SystemVerilog, simulation environments, and code coverage analysis is typically required, along with knowledge of industry standards. Strong leadership, project management, effective communication, and team-building abilities help set top candidates apart. These skills and qualities are critical to ensuring thorough verification cycles, timely project delivery, and successful cross-functional team collaboration in complex semiconductor development projects.

What are popular job titles related to Asic Verification Manager jobs in Oregon?

For Asic Verification Manager jobs in Oregon, the most frequently searched job titles are:

What job categories do people searching Asic Verification Manager jobs in Oregon look for?

The top searched job categories for Asic Verification Manager jobs in Oregon are:

Asic Verification Manager jobs near you
Infographic showing various Asic Verification Manager job openings in Oregon as of August 2026, with employment types broken down into 87% Full Time, and 13% Contract. Highlights an 87% In-person, and 13% Remote job distribution, with an average salary of $143,998 per year, or $69.2 per hour.

PE Logic Design

Rambus

Hillsboro, OR • Hybrid

$127K - $236K/yr

Full-time

Medical, Dental, Retirement

Posted 18 days ago

Job description

Rambus, a premier chip and silicon IP provider, is seeking to hire an exceptional Principal Logic Design Engineer to join our Silicon IP (SIP) team in Hillsboro, Oregon. Candidates will be joining some of the brightest inventors and engineers in the world to develop products that make data faster and safer. 

In this role, the candidate will be reporting to the Director of Engineering as an individual contributor. As a Principal Logic Design Engineer, you will play a pivotal role in the micro-architecture and design of our next- generation high performance and cutting-edge memory controllers for data centers and AI applications. This is a fast-growing market with high demand from tier-1 customers which gives ample opportunity for innovation and differentiation. If you like challenges and want to make a technical difference in the memory landscape during these exciting times in the semiconductor industry, this is the right opportunity for you. 

Rambus offers a flexible work environment, embracing a hybrid approach for most office-based roles. Employees are encouraged to spend an average of at least three days per week onsite, allowing for two days of remote work. 


  • Own micro-architecture definition and RTL design for critical blocks such as schedulers, command pipelines, coherency/ordering logic and system interfaces 
  • Analyze performance, power, and area (PPA) trade-offs and drive design decisions based on quantitative data 
  • Collaborate closely with verification team to shape test plans and improve verification coverage 
  • Work with physical design team to understand and resolve timing, power, and congestion challenges 
  • Work with verification team on regression failure debug and root cause, and provide RTL fix if necessary 
  • Provide technical support to FAE team on pre-sales customer engagements 
  • Provide technical support to AE team on post-sales customer deliveries 

  • Strong System Verilog/Verilog RTL design expertise 
  • Questa/Incisive/VCS simulator experience 
  • Python/Perl/TCL scripting experience 
  • Ability to learn quickly and work independently 
  • Solid communication and project management skills 
  • 10+ years of logic design experience (ASIC/FPGA) with BSEE, or  
  • 8+ years of logic design experience (ASIC/FPGA) with MSEE 

Definite Plus: 

  • ASIC synthesis, timing constraint, CDC/RDC experience 
  • UVM Verification experience 
  • Memory (HBM, LPDDR) expertise 
  • AMBA AXI or CHI design experience 

About Rambus 

Rambus is a global company that makes industry-leading memory interface chips and Silicon IP to advance data center connectivity and solve the bottleneck between memory and processing. With over 30 years of semiconductor experience, we are a leading provider of high-performance products and innovations that maximize the bandwidth, capacity and security for AI and other data-intensive workloads. Our world-class team is the foundation of our company, and our innovative spirit drives us to develop the cutting-edge products and technologies essential for tomorrow’s systems.  

Rambus offers a competitive compensation package including base salary, bonus, equity, matching 401(k), employee stock purchase plan, comprehensive medical and dental benefits, time-off program, and gym membership.  

The US salary range for this full-time position is $127,400 to $236,600

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