Description As an ASIC STA Engineer, you will have responsibilities spanning all aspects of SoC ... You will also come up with ideas and plans to verify your own timing constraints. You will innovate ...
Description As an ASIC STA Engineer, you will have responsibilities spanning all aspects of SoC ... You will also come up with ideas and plans to verify your own timing constraints. You will innovate ...
Description As an ASIC STA Engineer, you will have responsibilities spanning all aspects of SoC ... You will also come up with ideas and plans to verify your own timing constraints. You will innovate ...
Description As an ASIC STA Engineer, you will have responsibilities spanning all aspects of SoC ... You will also come up with ideas and plans to verify your own timing constraints. You will innovate ...
Timing Design Engineer
Beaverton, OR · On-site
Description As an ASIC STA Engineer, you will have responsibilities spanning all aspects of SoC ... You will also come up with ideas and plans to verify your own timing constraints. You will innovate ...
Timing Design Engineer
Beaverton, OR · On-site
Description As an ASIC STA Engineer, you will have responsibilities spanning all aspects of SoC ... You will also come up with ideas and plans to verify your own timing constraints. You will innovate ...
Principal Logic Design Engineer
Hillsboro, OR · On-site
$127.40 - $236.60/hr
Medical
Dental
Retirement
Solid communication and project management skills * 10+ years of logic design experience (ASIC/FPGA ... ASIC synthesis, timing constraint, CDC/RDC experience * UVM Verification experience * Memory (HBM ...
Principal Logic Design Engineer
Hillsboro, OR · On-site
$127.40 - $236.60/hr
Medical
Dental
Retirement
Solid communication and project management skills * 10+ years of logic design experience (ASIC/FPGA ... ASIC synthesis, timing constraint, CDC/RDC experience * UVM Verification experience * Memory (HBM ...
FPGA Engineering Manager (MTD, Tualatin, OR)
Tualatin, OR · On-site
$155K - $248K/yr
Medical
Dental
Vision
Life
Retirement
PTO
Minimum of 5 years of experience as an FPGA/ASIC project lead, driving multiple projects through ... Familiarity with digital verification tools and methodologies (preferably UVM). * Experience with ...
FPGA Engineering Manager (MTD, Tualatin, OR)
Tualatin, OR · On-site
$155K - $248K/yr
Medical
Dental
Vision
Life
Retirement
PTO
Minimum of 5 years of experience as an FPGA/ASIC project lead, driving multiple projects through ... Familiarity with digital verification tools and methodologies (preferably UVM). * Experience with ...
FPGA Engineering Manager (MTD, Tualatin, OR)
Tualatin, OR · On-site
$155K - $248K/yr
Medical
Dental
Vision
Life
Retirement
PTO
Minimum of 5 years of experience as an FPGA/ASIC project lead, driving multiple projects through ... Familiarity with digital verification tools and methodologies (preferably UVM). * Experience with ...
FPGA Engineering Manager (MTD, Tualatin, OR)
Tualatin, OR · On-site
$155K - $248K/yr
Medical
Dental
Vision
Life
Retirement
PTO
Minimum of 5 years of experience as an FPGA/ASIC project lead, driving multiple projects through ... Familiarity with digital verification tools and methodologies (preferably UVM). * Experience with ...
Principal Logic Design Engineer
Hillsboro, OR · Hybrid
$127K - $236K/yr
Medical
Dental
Retirement
Solid communication and project management skills * 10+ years of logic design experience (ASIC/FPGA ... ASIC synthesis, timing constraint, CDC/RDC experience * UVM Verification experience * Memory (HBM ...
Principal Logic Design Engineer
Hillsboro, OR · Hybrid
$127K - $236K/yr
Medical
Dental
Retirement
Solid communication and project management skills * 10+ years of logic design experience (ASIC/FPGA ... ASIC synthesis, timing constraint, CDC/RDC experience * UVM Verification experience * Memory (HBM ...
Principal Logic Design Engineer
Hillsboro, OR · On-site
$127K - $236K/yr
Medical
Dental
Retirement
Solid communication and project management skills * 10+ years of logic design experience (ASIC/FPGA ... ASIC synthesis, timing constraint, CDC/RDC experience * UVM Verification experience * Memory (HBM ...
Principal Logic Design Engineer
Hillsboro, OR · On-site
$127K - $236K/yr
Medical
Dental
Retirement
Solid communication and project management skills * 10+ years of logic design experience (ASIC/FPGA ... ASIC synthesis, timing constraint, CDC/RDC experience * UVM Verification experience * Memory (HBM ...
Principal Logic Design Engineer
Hillsboro, OR · Hybrid
$127K - $236K/yr
Medical
Dental
Retirement
Solid communication and project management skills * 10+ years of logic design experience (ASIC/FPGA ... ASIC synthesis, timing constraint, CDC/RDC experience * UVM Verification experience * Memory (HBM ...
Principal Logic Design Engineer
Hillsboro, OR · Hybrid
$127K - $236K/yr
Medical
Dental
Retirement
Solid communication and project management skills * 10+ years of logic design experience (ASIC/FPGA ... ASIC synthesis, timing constraint, CDC/RDC experience * UVM Verification experience * Memory (HBM ...
Principal Logic Design Engineer
Hillsboro, OR · On-site
$127K - $236K/yr
Medical
Dental
Retirement
Solid communication and project management skills * 10+ years of logic design experience (ASIC/FPGA ... ASIC synthesis, timing constraint, CDC/RDC experience * UVM Verification experience * Memory (HBM ...
Principal Logic Design Engineer
Hillsboro, OR · On-site
$127K - $236K/yr
Medical
Dental
Retirement
Solid communication and project management skills * 10+ years of logic design experience (ASIC/FPGA ... ASIC synthesis, timing constraint, CDC/RDC experience * UVM Verification experience * Memory (HBM ...
Director, Engineering
Hillsboro, OR · On-site
Medical
Retirement
PTO
... and ASIC/Foundry products.Partner closely with Architecture, Circuit Design, RTL Design, Verification, Package, Product Engineering, and Technology Development teams.Manage schedule, resource ...
Director, Engineering
Hillsboro, OR · On-site
Medical
Retirement
PTO
... and ASIC/Foundry products.Partner closely with Architecture, Circuit Design, RTL Design, Verification, Package, Product Engineering, and Technology Development teams.Manage schedule, resource ...
Familiarity with hardware development workflows (modeling, verification, or similar) * Up to date ... Familiarity with GPU or ASIC development processes * Experience with configuration management for ...
Familiarity with hardware development workflows (modeling, verification, or similar) * Up to date ... Familiarity with GPU or ASIC development processes * Experience with configuration management for ...
OR · On-site
Familiarity with hardware development workflows (modeling, verification, or similar) * Up to date ... Familiarity with GPU or ASIC development processes * Experience with configuration management for ...
Hardware Design Engineer
Hillsboro, OR · Hybrid
$106K - $198K/yr
Medical
Dental
Retirement
Solid communication and project management skills * 5+ years of logic design experience * BSEE Definite Plus: * ASIC synthesis, timing constraint, CDC/RDC experience * Verification experience
Hardware Design Engineer
Hillsboro, OR · Hybrid
$106K - $198K/yr
Medical
Dental
Retirement
Solid communication and project management skills * 5+ years of logic design experience * BSEE Definite Plus: * ASIC synthesis, timing constraint, CDC/RDC experience * Verification experience
Hardware Design Engineer
Hillsboro, OR · Hybrid
$106K - $198K/yr
Medical
Dental
Retirement
Solid communication and project management skills * 5+ years of logic design experience * BSEE Definite Plus: * ASIC synthesis, timing constraint, CDC/RDC experience * Verification experience
Hardware Design Engineer
Hillsboro, OR · Hybrid
$106K - $198K/yr
Medical
Dental
Retirement
Solid communication and project management skills * 5+ years of logic design experience * BSEE Definite Plus: * ASIC synthesis, timing constraint, CDC/RDC experience * Verification experience
Hardware Design Engineer
Hillsboro, OR · On-site
$106K - $198K/yr
Medical
Dental
Retirement
Solid communication and project management skills * 5+ years of logic design experience * BSEE Definite Plus: * ASIC synthesis, timing constraint, CDC/RDC experience * Verification experience
Hardware Design Engineer
Hillsboro, OR · On-site
$106K - $198K/yr
Medical
Dental
Retirement
Solid communication and project management skills * 5+ years of logic design experience * BSEE Definite Plus: * ASIC synthesis, timing constraint, CDC/RDC experience * Verification experience
Hardware Design Engineer
Hillsboro, OR · On-site
$106K - $198K/yr
Medical
Dental
Retirement
Solid communication and project management skills * 5+ years of logic design experience * BSEE Definite Plus: * ASIC synthesis, timing constraint, CDC/RDC experience * Verification experience
Hardware Design Engineer
Hillsboro, OR · On-site
$106K - $198K/yr
Medical
Dental
Retirement
Solid communication and project management skills * 5+ years of logic design experience * BSEE Definite Plus: * ASIC synthesis, timing constraint, CDC/RDC experience * Verification experience
EDA Tools SW Engineer
Hillsboro, OR · On-site
$173K - $330K/yr
Medical
Retirement
PTO
... ASIC tools/flows and Physical verification/runsets, Tape-in Verification and IP sign off for test ... Technical management or lead experience mentoring or leading medium sized teams. * Experience with ...
EDA Tools SW Engineer
Hillsboro, OR · On-site
$173K - $330K/yr
Medical
Retirement
PTO
... ASIC tools/flows and Physical verification/runsets, Tape-in Verification and IP sign off for test ... Technical management or lead experience mentoring or leading medium sized teams. * Experience with ...
EDA Tools SW Engineer
Hillsboro, OR · Hybrid
$173K - $330K/yr
Medical
Retirement
PTO
... ASIC tools/flows and Physical verification/runsets, Tape-in Verification and IP sign off for test ... Technical management or lead experience mentoring or leading medium sized teams. * Experience with ...
EDA Tools SW Engineer
Hillsboro, OR · Hybrid
$173K - $330K/yr
Medical
Retirement
PTO
... ASIC tools/flows and Physical verification/runsets, Tape-in Verification and IP sign off for test ... Technical management or lead experience mentoring or leading medium sized teams. * Experience with ...
FPGA/RTL Design Engineer - III (W2 Only)
$134K - $184K/yr
... managed services and direct placement services to Global 2000 Corporations. Collabera is ranked ... verification collaterals Working with the physical design team for floor-plan and timing ...
FPGA/RTL Design Engineer - III (W2 Only)
$134K - $184K/yr
... managed services and direct placement services to Global 2000 Corporations. Collabera is ranked ... verification collaterals Working with the physical design team for floor-plan and timing ...
Asic Verification Manager information
See Oregon salary details
$26.9K - $44.4K
11% of jobs
$44.4K - $61.8K
6% of jobs
$61.8K - $79.3K
2% of jobs
$79.3K - $96.7K
5% of jobs
$103.3K is the 25th percentile. Wages below this are outliers.
$96.7K - $114.2K
2% of jobs
$114.2K - $131.7K
6% of jobs
$131.7K - $149.1K
7% of jobs
The median wage is $162.9K / yr.
$149.1K - $166.6K
13% of jobs
$166.6K - $184K
19% of jobs
$186.6K is the 75th percentile. Wages above this are outliers.
$184K - $201.5K
23% of jobs
$201.5K - $218.9K
5% of jobs
$26.9K
$144K
$218.9K
How much do asic verification manager jobs pay per year?
As of Aug 17, 2026, the average yearly pay for asic verification manager in Oregon is $143,998.00, according to ZipRecruiter salary data. Most workers in this role earn between $94,753.00 and $189,507.00 per year, depending on experience, location, and employer.
What does an Asic Verification Manager do?
An ASIC Verification Manager leads a team responsible for verifying the functionality and performance of ASIC designs before production. They develop verification strategies, oversee testbench creation, and ensure compliance with design specifications. Their role includes managing project timelines, collaborating with design and software teams, and improving verification methodologies. Strong leadership, technical expertise in verification tools, and experience in UVM and SystemVerilog are essential for success in this role.
What are some of the primary challenges faced by Asic Verification Managers in their daily work?
ASIC Verification Managers often navigate the complexities of verifying highly integrated, feature-rich designs under tight development timelines. They manage large teams of engineers, coordinate cross-functional communication with design, physical implementation, and firmware groups, and are responsible for developing and executing comprehensive verification plans. Balancing resource allocation, ensuring thorough test coverage, and adapting to evolving project requirements are common challenges. Success in this role often depends on strong organizational skills, attention to technical detail, and the ability to anticipate and resolve verification bottlenecks promptly.
What are the key skills and qualifications needed to thrive in the Asic Verification Manager position, and why are they important?
To thrive as an ASIC Verification Manager, you need a deep understanding of digital design and verification methodologies, experience with hardware description languages (HDLs) such as Verilog or VHDL, and a degree in electrical engineering or a related field. Familiarity with verification tools like UVM, SystemVerilog, simulation environments, and code coverage analysis is typically required, along with knowledge of industry standards. Strong leadership, project management, effective communication, and team-building abilities help set top candidates apart. These skills and qualities are critical to ensuring thorough verification cycles, timely project delivery, and successful cross-functional team collaboration in complex semiconductor development projects.
What are popular job titles related to Asic Verification Manager jobs in Oregon?
For Asic Verification Manager jobs in Oregon, the most frequently searched job titles are:
What job categories do people searching Asic Verification Manager jobs in Oregon look for?
The top searched job categories for Asic Verification Manager jobs in Oregon are:
Apple rating
8.0
Based on 677 frontline employees who took The Breakroom Quiz
7th of 30 rated technology retailers
Job description
Apple is where individual imaginations gather together, committing to the values that lead to great work. Every new product we build, service we create, or Apple Store experience we deliver is the result of us making each other’s ideas stronger. That happens because every one of us shares a belief that we can make something wonderful and share it with the world, changing lives for the better. It’s the diversity of our people and their thinking that encourages the innovation that runs through everything we do. When we bring everybody in, we can do the best work of our lives. Here, you’ll do more than join something - you’ll add something.
Description
As an ASIC STA Engineer, you will have responsibilities spanning all aspects of SoC design in terms of timing. Key responsibilities include timing sign-off, STA and sign-off flow development, ownership of IP and block level timing constraints both for regular and custom timing requirements from synthesis to sign-off to achieve sign-off quality timing constraints. You will closely interact with RTL designer to understand design intent and clock structure, with CAD to understand and develop flow, and with Physical design team to close and sign-off timing. You will also come up with ideas and plans to verify your own timing constraints. You will innovate timing constraints and flow to facilitate timing closure and any potential pessimism or fall outs in timing analysis.
Preferred Qualifications
This position requires detailed knowledge of the ASIC design timing closure flow and methodology.
The ideal candidate will have at least 2+ years of experience in writing ASIC timing constraints and timing closure, expertise in STA tools (Primetime) and flow, knowledge of timing corners/modes, process variations and signal integrity related issues, hands on experience in timing/SDC constraints generation and management, proficient in scripting languages (Tcl and Perl), Familiarity with synthesis, DFT and backend related methodology and tools.
Strong communication skills are a pre-requisite. You will be collaborating with many diverse groups at Apple.
The ideal candidate will be a self starter and highly motivated to be successful at Apple.
Minimum Qualifications
BS degree in technical discipline with minimum 10 years of proven experience.
Description
As an ASIC STA Engineer, you will have responsibilities spanning all aspects of SoC design in terms of timing. Key responsibilities include timing sign-off, STA and sign-off flow development, ownership of IP and block level timing constraints both for regular and custom timing requirements from synthesis to sign-off to achieve sign-off quality timing constraints. You will closely interact with RTL designer to understand design intent and clock structure, with CAD to understand and develop flow, and with Physical design team to close and sign-off timing. You will also come up with ideas and plans to verify your own timing constraints. You will innovate timing constraints and flow to facilitate timing closure and any potential pessimism or fall outs in timing analysis.
Preferred Qualifications
This position requires detailed knowledge of the ASIC design timing closure flow and methodology.
The ideal candidate will have at least 2+ years of experience in writing ASIC timing constraints and timing closure, expertise in STA tools (Primetime) and flow, knowledge of timing corners/modes, process variations and signal integrity related issues, hands on experience in timing/SDC constraints generation and management, proficient in scripting languages (Tcl and Perl), Familiarity with synthesis, DFT and backend related methodology and tools.
Strong communication skills are a pre-requisite. You will be collaborating with many diverse groups at Apple.
The ideal candidate will be a self starter and highly motivated to be successful at Apple.
Minimum Qualifications
BS degree in technical discipline with minimum 10 years of proven experience.
About Apple
Sourced by ZipRecruiter
Imagine what you could do here! At Apple, new ideas have a way of becoming extraordinary products, services, and customer experiences very quickly. Bring passion and dedication to your job and there's no telling what you could accomplish. Dynamic, intelligent people and inspiring, innovative technologies are the norm here. The people who work here have reinvented entire industries with all Apple Hardware products. The same real passion for innovation that goes into our products also applies to our practices strengthening our dedication to leave the world better than we found it.
Industry
Computer and electronic product manufacturing
Company size
10,000+ Employees
Headquarters location
Cupertino, CA, US
Year founded
1976