Are you looking for a Mask layout Design Engineer role? We are seeking a hands-on Senior SRAM Layout Engineer to lead the physical layout creation for SRAM and memory IP in advanced CMOS nodes. In ...
Are you looking for a Mask layout Design Engineer role? We are seeking a hands-on Senior SRAM Layout Engineer to lead the physical layout creation for SRAM and memory IP in advanced CMOS nodes. In ...
We have an extraordinary opportunity for Circuits Engineers to design advanced custom digital megacells (SRAM memories, on-chip sensors, ML accelerators data path) used in a high performance / low ...
We have an extraordinary opportunity for Circuits Engineers to design advanced custom digital megacells (SRAM memories, on-chip sensors, ML accelerators data path) used in a high performance / low ...
... SRAM design basics, multiple clock/power domains and power management strategies, prefetchers ... programming Experience using an interpretive language such as Perl or Python
... SRAM design basics, multiple clock/power domains and power management strategies, prefetchers ... programming Experience using an interpretive language such as Perl or Python
... SRAM design basics, multiple clock/power domains and power management strategies, prefetchers ... programming Experience using an interpretive language such as Perl or Python
... SRAM design basics, multiple clock/power domains and power management strategies, prefetchers ... programming Experience using an interpretive language such as Perl or Python
Custom Circuits Design Engineer
$150K - $277K/yr
We have an extraordinary opportunity for Circuits Engineers to design advanced custom digital megacells (SRAM memories, on-chip sensors, ML accelerators data path) used in a high performance / low ...
Custom Circuits Design Engineer
$150K - $277K/yr
We have an extraordinary opportunity for Circuits Engineers to design advanced custom digital megacells (SRAM memories, on-chip sensors, ML accelerators data path) used in a high performance / low ...
Custom Circuits Design Engineer
$150K - $277K/yr
We have an extraordinary opportunity for Circuits Engineers to design advanced custom digital megacells (SRAM memories, on-chip sensors, ML accelerators data path) used in a high performance / low ...
Custom Circuits Design Engineer
$150K - $277K/yr
We have an extraordinary opportunity for Circuits Engineers to design advanced custom digital megacells (SRAM memories, on-chip sensors, ML accelerators data path) used in a high performance / low ...
CPU Cache Microarchitect/RTL Engineer
$184K - $324K/yr
... SRAM design basics, multiple clock/power domains and power management strategies, prefetchers ... C++ programming Experience using an interpretive language such as Perl or Python Minimum ...
CPU Cache Microarchitect/RTL Engineer
$184K - $324K/yr
... SRAM design basics, multiple clock/power domains and power management strategies, prefetchers ... C++ programming Experience using an interpretive language such as Perl or Python Minimum ...
CPU Cache Microarchitect/RTL Engineer
$184K - $324K/yr
... SRAM design basics, multiple clock/power domains and power management strategies, prefetchers ... C++ programming Experience using an interpretive language such as Perl or Python Minimum ...
CPU Cache Microarchitect/RTL Engineer
$184K - $324K/yr
... SRAM design basics, multiple clock/power domains and power management strategies, prefetchers ... C++ programming Experience using an interpretive language such as Perl or Python Minimum ...
CPU Cache Microarchitect/RTL Engineer
$184K - $324K/yr
... SRAM design basics, multiple clock/power domains and power management strategies, prefetchers ... C++ programming Experience using an interpretive language such as Perl or Python Minimum ...
CPU Cache Microarchitect/RTL Engineer
$184K - $324K/yr
... SRAM design basics, multiple clock/power domains and power management strategies, prefetchers ... C++ programming Experience using an interpretive language such as Perl or Python Minimum ...
CPU Cache Microarchitect/RTL Engineer
$184K - $324K/yr
... SRAM design basics, multiple clock/power domains and power management strategies, prefetchers ... C++ programming Experience using an interpretive language such as Perl or Python Minimum ...
CPU Cache Microarchitect/RTL Engineer
$184K - $324K/yr
... SRAM design basics, multiple clock/power domains and power management strategies, prefetchers ... C++ programming Experience using an interpretive language such as Perl or Python Minimum ...
CPU Cache Microarchitect/RTL Engineer
$184K - $324K/yr
... SRAM design basics, multiple clock/power domains and power management strategies, prefetchers ... C++ programming Experience using an interpretive language such as Perl or Python Minimum ...
CPU Cache Microarchitect/RTL Engineer
$184K - $324K/yr
... SRAM design basics, multiple clock/power domains and power management strategies, prefetchers ... C++ programming Experience using an interpretive language such as Perl or Python Minimum ...
CPU Cache Microarchitect/RTL Engineer
$184K - $324K/yr
... SRAM design basics, multiple clock/power domains and power management strategies, prefetchers ... C++ programming Experience using an interpretive language such as Perl or Python Minimum ...
CPU Cache Microarchitect/RTL Engineer
$184K - $324K/yr
... SRAM design basics, multiple clock/power domains and power management strategies, prefetchers ... C++ programming Experience using an interpretive language such as Perl or Python Minimum ...
Master degree in Electrical Engineering, Computer Engineering, Electrical and Computer Engineering ... Design, characterization, and verification of custom memory circuits such as SRAM, Register Files ...
Master degree in Electrical Engineering, Computer Engineering, Electrical and Computer Engineering ... Design, characterization, and verification of custom memory circuits such as SRAM, Register Files ...
Master degree in Electrical Engineering, Computer Engineering, Electrical and Computer Engineering ... Design, characterization, and verification of custom memory circuits such as SRAM, Register Files ...
Master degree in Electrical Engineering, Computer Engineering, Electrical and Computer Engineering ... Design, characterization, and verification of custom memory circuits such as SRAM, Register Files ...
Analog and Mixed Signal Design Engineer
Hillsboro, OR · On-site
$164K - $269K/yr
... SRAM, RF, ROM, eDRAM, Fuse, etc.), Analog Circuit Reference Designs (PLL, BGR, ADC, etc.), High ... Work closely with process and IP engineers to anticipate AMS IP requirements and use design and ...
Analog and Mixed Signal Design Engineer
Hillsboro, OR · On-site
$164K - $269K/yr
... SRAM, RF, ROM, eDRAM, Fuse, etc.), Analog Circuit Reference Designs (PLL, BGR, ADC, etc.), High ... Work closely with process and IP engineers to anticipate AMS IP requirements and use design and ...
Analog and Mixed Signal Design Engineer
Hillsboro, OR · On-site
$164K - $269K/yr
... SRAM, RF, ROM, eDRAM, Fuse, etc.), Analog Circuit Reference Designs (PLL, BGR, ADC, etc.), High ... Work closely with process and IP engineers to anticipate AMS IP requirements and use design and ...
Analog and Mixed Signal Design Engineer
Hillsboro, OR · On-site
$164K - $269K/yr
... SRAM, RF, ROM, eDRAM, Fuse, etc.), Analog Circuit Reference Designs (PLL, BGR, ADC, etc.), High ... Work closely with process and IP engineers to anticipate AMS IP requirements and use design and ...
Collateral Design and DFM Engineer
$140K - $168K/yr
Position Overview As a Collateral - Design and DFM Lead Engineer you will be at the heart of HVM ... Strong understanding of DTCO skills including understanding of SRAM, Standard cells, Process ...
Collateral Design and DFM Engineer
$140K - $168K/yr
Position Overview As a Collateral - Design and DFM Lead Engineer you will be at the heart of HVM ... Strong understanding of DTCO skills including understanding of SRAM, Standard cells, Process ...
Design and develop digital hardware circuits Integrating embedded processors, switch ASICs, DDR4 or ... SRAM, and supporting digital logic * Create schematics and guide PCB layout with attention to ...
Quick apply
Design and develop digital hardware circuits Integrating embedded processors, switch ASICs, DDR4 or ... SRAM, and supporting digital logic * Create schematics and guide PCB layout with attention to ...
Software Research Engineer/Scientist
Hillsboro, OR · On-site
$201K - $284K/yr
... design layout for standard cell libraries, place and route, SRAM, or analog mixed signals • Some experience with development of automation flows to enable DTCO acceleration Job Type: Experienced ...
Software Research Engineer/Scientist
Hillsboro, OR · On-site
$201K - $284K/yr
... design layout for standard cell libraries, place and route, SRAM, or analog mixed signals • Some experience with development of automation flows to enable DTCO acceleration Job Type: Experienced ...
Software Research Engineer/Scientist
Hillsboro, OR · On-site
$201K - $284K/yr
Degree in Engineering, Physical Science, Computer Science, or related fields. 3+ years of ... design layout for standard cell libraries, place and route, SRAM, or analog mixed signals Some ...
Software Research Engineer/Scientist
Hillsboro, OR · On-site
$201K - $284K/yr
Degree in Engineering, Physical Science, Computer Science, or related fields. 3+ years of ... design layout for standard cell libraries, place and route, SRAM, or analog mixed signals Some ...
Sram Design Engineer information
See Oregon salary details
$19.06 - $24.40
1% of jobs
$24.40 - $29.74
2% of jobs
$29.74 - $35.07
7% of jobs
$35.07 - $40.41
11% of jobs
$41.95 is the 25th percentile. Wages below this are outliers.
$40.41 - $45.75
14% of jobs
$45.75 - $51.08
15% of jobs
The median wage is $51.29 / hr.
$51.08 - $56.42
14% of jobs
$56.42 - $61.76
8% of jobs
$63.34 is the 75th percentile. Wages above this are outliers.
$61.76 - $67.10
12% of jobs
$67.10 - $72.43
12% of jobs
$72.43 - $77.77
5% of jobs
$19
$53
$77
How much do sram design engineer jobs pay per hour?
As of Jul 6, 2026, the average hourly pay for sram design engineer in Oregon is $53.59, according to ZipRecruiter salary data. Most workers in this role earn between $41.44 and $65.34 per hour, depending on experience, location, and employer.
What are the key skills and qualifications needed to thrive in the Sram Design Engineer position, and why are they important?
To thrive as a Sram Design Engineer, a strong background in electrical engineering, VLSI design, and semiconductor device physics—often supported by a relevant bachelor’s or master’s degree—is essential. Expertise in industry-standard EDA tools like Cadence, Synopsys, and Mentor Graphics, as well as experience with HDL languages such as Verilog or VHDL, is typically required. Attention to detail, problem-solving skills, and the ability to communicate effectively with cross-functional teams are important soft skills for the role. These skills ensure high-quality SRAM design, efficient collaboration, and the ability to meet both performance and reliability targets in advanced integrated circuits.
What are the typical daily responsibilities of a Sram Design Engineer?
As a Sram Design Engineer, your daily tasks often include designing and verifying static random-access memory (SRAM) circuits, running simulations to validate performance, and troubleshooting design issues. You’ll collaborate closely with layout engineers, verification teams, and other design engineers to optimize memory architectures and ensure compliance with power, area, and timing specifications. Additionally, you may attend design reviews, document design methodologies, and interact with foundries during tape-out or silicon validation phases. This role frequently involves both independent technical work and teamwork within a multidisciplinary environment focused on delivering high-performance semiconductor products.
What is an SRAM Design Engineer job?
An SRAM Design Engineer is responsible for designing Static Random-Access Memory (SRAM) circuits used in semiconductor chips. They focus on optimizing performance, power consumption, and area efficiency while ensuring reliable functionality. Their work includes transistor-level design, layout, simulation, and verification of SRAM cells, sense amplifiers, and peripheral circuits. They collaborate with process engineers and digital designers to integrate SRAM into larger systems. Strong knowledge of VLSI design, circuit theory, and semiconductor technology is essential for this role.
What are popular job titles related to Sram Design Engineer jobs in Oregon? For Sram Design Engineer jobs in Oregon, the most frequently searched job titles are:
What job categories do people searching Sram Design Engineer jobs in Oregon look for? The top searched job categories for Sram Design Engineer jobs in Oregon are:
What cities in Oregon are hiring for Sram Design Engineer jobs? Cities in Oregon with the most Sram Design Engineer job openings:
Job description
NVIDIA has been transforming computer graphics, PC gaming, and accelerated computing for more than 25 years. It's a unique legacy of innovation that's fueled by great technology-and amazing people. Today, we're tapping into the unlimited potential of AI to define the next era of computing. An era in which our GPU acts as the brains of computers, robots, and self-driving cars that can understand the world. Doing what's never been done before takes vision, innovation, and the world's best talent. As an NVIDIAN, you'll be immersed in a diverse, supportive environment where everyone is inspired to do their best work. Come join the team and see how you can make a lasting impact on the world.
Are you looking for a Mask layout Design Engineer role? We are seeking a hands-on Senior SRAM Layout Engineer to lead the physical layout creation for SRAM and memory IP in advanced CMOS nodes. In this role, you will build custom memory layouts from initial floorplanning through DRC/LVS-clean tapeout, working closely with circuit design, physical design, integration, CAD, and foundry teams. This is a senior individual contributor role for someone who can produce complex layouts, make informed advanced-node tradeoffs, improve layout methodology, and guide junior engineers.
What you will be doing:
Manage the complete custom layout process for SRAM bitcell arrays, memory periphery, test structures, and memory macros in advanced CMOS technologies.
Develop and improve floorplans for SRAM and memory blocks, covering array layout, periphery positioning, power grid design, routing channels, and macro assembly.
Carry out, debug, and complete DRC, LVS, ERC, antenna, and associated physical verification checks with tools such as Calibre, ICV, or similar workflows.
Support EM/IR review, power integrity, density/fill, DFM, dummy insertion, layout-dependent effects, and other requirements for tapeout.
Collaborate with circuit designers to convert schematics into layouts, ensuring matching, symmetry, shielding, parasitic targets, and reliability constraints are maintained.
Collaborate with PnR and integration teams to resolve top-level DRC/LVS, pin access, boundary, routing, power-grid, and macro-integration issues.
Implement and advance layout methodology, checklists, reusable practices, and quality standards for consistent memory IP delivery.
Collaborate with foundry, CAD, and methodology teams on rule interpretation, deck behavior, waivers, and advanced-node process constraints.
Review layouts, mentor junior engineers, and help raise layout quality and execution rigor across the team.
What we need to see:
Have a BSEE or equivalent experience
10+ years of custom IC layout experience, including 5+ years in SRAM, memory compiler, or full-custom memory IP layout.
Hands-on participation in advanced CMOS technology initiatives, preferably concentrating on FinFET or GAA nodes at 5nm, 3nm, or smaller dimensions.
Solid grasp of SRAM and memory layout principles.
Extensive experience in Cadence Virtuoso applied to custom layout creation and assessment.
Extensive experience in DRC/LVS debugging using Calibre, ICV, or similar physical verification tools.
Experience with floorplanning, block-level routing, macro assembly, pin planning, boundary/interface management, and top-level physical verification.
Direct familiarity with advanced-node layout limitations and layout-dependent phenomena, including LOD, density/fill, matching, symmetry, shielding, electromigration, IR drop, and DFM or similar expertise.
Ability to work effectively with circuit build, physical build, integration, CAD, and foundry teams.
Clear communication, strong ownership, good judgment, and the ability to mentor other engineers.
Ways to stand out from the crowd:
Experience in scripting using Cadence SKILL, Python, or comparable languages for layout automation, checks, reporting, or improving workflows.
Strong familiarity with EM/IR, reliability, density, fill, DFM, and post-processing closure at both IP and top level.
Widely considered to be one of the technology world's most desirable employers, NVIDIA offers highly competitive salaries and a comprehensive benefits package. As you plan your future, see what we can offer to you and your family www.nvidiabenefits.com/
#LI-Hybrid
You will also be eligible for equity and benefits.
This posting is for an existing vacancy.
NVIDIA uses AI tools in its recruiting processes.
NVIDIA is committed to fostering an inclusive work environment and proud to be an equal opportunity employer. As we highly value diversity in our current and future employees, we do not discriminate (including in our hiring and promotion practices) on the basis of race, religion, color, national origin, gender, gender expression, sexual orientation, age, marital status, veteran status, disability status or any other characteristic protected by law.
About Nvidia
Sourced by ZipRecruiter
NVIDIA has been transforming computer graphics, PC gaming, and accelerated computing for more than 25 years. It's a unique legacy of innovation that's fueled by great technology--and amazing people. Today, we're tapping into the unlimited potential of AI to define the next era of computing. An era in which our GPU acts as the brains of computers, robots, and self-driving cars that can understand the world. Doing what's never been done before takes vision, innovation, and the world's best talent.
Industry
Computer and electronic product manufacturing
Company size
10,000+ Employees
Headquarters location
Santa Clara, CA, US
Year founded
1993