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Asic Physical Design Engineer Jobs (NOW HIRING)

Cisco

ASIC Physical Design Engineer

Austin, TX

$135.80K - $195.10K/yr

Your Impact As a Physical Design Engineer with Acacia, you will focus on the technical execution of high-performance ASIC designs. Working as an individual contributor, you will lead the RTL-to-GDSII ...

Ericsson

Developer (Physical Design Engineer)

Austin, TX · On-site

$134.80K - $138.80K/yr

... Design Engineer) in Austin, TX; Hybrid work policy w/in commuting distance, who will serve to ... ASIC physical design optimization through synthesis, place and route; (or) ASIC physical design ...

Cisco

ASIC Physical Design Engineer

Maynard, MA

$135.80K - $195.10K/yr

Your Impact As a Physical Design Engineer with Acacia, you will focus on the technical execution of high-performance ASIC designs. Working as an individual contributor, you will lead the RTL-to-GDSII ...

The PJF Group

Physical Design Engineer

Bodega Bay, CA

$161.40K - $166.10K/yr

We're looking for a hands-on Physical Design Engineer to support complex SoC projects for our ... Profile of preferred candidate includes 10 + years of hands-on experience, custom ASIC, strong ...

The PJF Group

Physical Design Engineer

Bodega Bay, CA · On-site

$180K - $230K/yr

We're looking for a hands-on Physical Design Engineer to support complex SoC projects for our ... Profile of preferred candidate includes 10 + years of hands-on experience, custom ASIC, strong ...

MatX

ASIC/SOC CAD Engineer

Mountain View, CA · On-site +1

$175K - $362.50K/yr

MatX is seeking a Physical Design CAD Engineer to join our team as we create best-in-class silicon for high-performance and sustainable GenAI. The ASIC/SOC Physically Design CAD Engineer will be ...

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How much do asic physical design engineer jobs pay per year?

As of Jun 1, 2026, the average yearly pay for asic physical design engineer in the United States is $139,408.00, according to ZipRecruiter salary data. Most workers in this role earn between $136,000.00 and $140,000.00 per year, depending on experience, location, and employer.

What is an ASIC Physical Design Engineer job?

An ASIC Physical Design Engineer is responsible for the back-end design and implementation of integrated circuits (ICs). They handle tasks such as floorplanning, placement, routing, timing closure, power optimization, and Design for Manufacturability (DFM). Using Electronic Design Automation (EDA) tools, they ensure the IC meets performance, power, and area (PPA) requirements. They collaborate with front-end design, verification, and fabrication teams to ensure a successful chip tape-out.

What are the key skills and qualifications needed to thrive in the Asic Physical Design Engineer position, and why are they important?

As an ASIC Physical Design Engineer, you need strong expertise in digital design, timing analysis, and semiconductor technology, often supported by a degree in electrical or computer engineering. Familiarity with EDA tools like Cadence, Synopsys, and Mentor Graphics for place-and-route, as well as relevant certifications in VLSI design, are highly valuable. Attention to detail, effective communication, and problem-solving abilities distinguish top professionals in this field. These competencies are crucial for ensuring accurate, efficient, and manufacturable ASIC designs in a fast-paced technological environment.

What are the typical daily responsibilities of an ASIC Physical Design Engineer?

As an ASIC Physical Design Engineer, your daily tasks often include translating RTL designs into physical layouts, performing place-and-route, running static timing analysis, and optimizing power, performance, and area metrics. You will frequently collaborate with design, verification, and fabrication teams to address design challenges and ensure seamless integration of IP blocks. Regular project meetings, documentation of design processes, and participation in design reviews are also common. This role involves balancing technical precision with teamwork, making communication skills and adaptability essential for success.
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Asic Physical Design Engineer jobs near you
Infographic showing various Asic Physical Design Engineer job openings in the United States as of May 2026, with employment types broken down into 100% Full Time. Highlights an 80% In-person, and 20% Remote job distribution, with an average salary of $139,408 per year, or $67 per hour.
ASIC Physical Design Engineer

ASIC Physical Design Engineer

Hewlett Packard Enterprise

San Jose, CA • Hybrid

$159.40K - $164.10K/yr

Full-time

Posted 23 days ago

Hewlett Packard Enterprise rating

8.3

Company rating: 8.3 out of 10

Based on 23 frontline employees who took The Breakroom Quiz

31st of 137 rated electronics manufacturers

Job description

ASIC Physical Design EngineerThis role has been designed as 'Hybrid' with an expectation that you will work on average 2 days per week from an HPE office.

Who We Are:

Hewlett Packard Enterprise is the global edge-to-cloud company advancing the way people live and work. We help companies connect, protect, analyze, and act on their data and applications wherever they live, from edge to cloud, so they can turn insights into outcomes at the speed required to thrive in today's complex world.Our culture thrives onfinding new and better ways to accelerate what's next.We know varied backgrounds are valued and succeed here. We have the flexibility to manage our work and personal needs.We make bold moves, together, and are a force for good. If you are looking to stretch and grow your career our culture will embrace you.Open up opportunities with HPE.

Job Description:

As ablock-levelPhysical Design Engineer, you will contribute to all phases of physical design from RTL to the delivery of our final GDSII. Your responsibilities include:

Responsibilities:

  • Implement physical design at thelargeSoC block level from RTL to GDSII, creating a design database ready for manufacturing.

  • Interact with IP vendors to understand IP integration requirements and integrate all blocks, IPs, andsub-chipsat a large SoC level.

  • Collaborate with the packaging team onMicrobump/Probe Bump/Bump/Pad placement.

  • Build block level floorplan, including block pins, macro placement and alignment, power grid, etc.

  • Develop the block-level clock network and clock structure in collaboration with clock experts.

  • generating block/chip-level static timing constraints.

  • Arrange, analyze, andoptimizefeedthrough and repeaters among all blocks

  • Perform block-level place and route,including customplace & route,ensuring the design meets timing, area, power constraints, and all sign-off criteria.

  • Generate and implement ECOs to fix timing, signal integrity, EM/IR violations, PV, and complete formal verification.

  • Integrate DFT into physical design, ensuring alignment with overall test strategies and manufacturing requirements.

  • Run Physical Design verification flow at chip/block level, fixing LVS/DRC/ERC/ANT violations.

  • Collaborate closely with architecture, frontend design, DV, and package teams to ensure cohesive design implementation and successful projecttapeouts.

Minimum Qualifications:

Education:

  • BS degree in electrical engineering, computer engineering, or a related field with 3+ years of experience in block or full-chip physical design, or

  • MS degree in the above fields with 2+ years of related experience.

Technical Expertise:

  • Deep design experience in large SoC designs, including IP integration.

  • Extensive knowledge and practices in Physical Design, including physically aware synthesis, floor-planning, place & route, CTS, and repeater/feedthrough.

  • Experience in implementing power-grid and clocknetworkat block level.

  • Knowledge of basic SoC architecture and HDL languages like Verilog to work with the logic design team for timing fixes.

  • Experience in physical design verification to debug LVS/DRC/ERC/ANT issues at chip/block level.

  • Experience in custom place and route.

  • Exposure to 2.5D/3D packaging is preferred.

  • High performance and large chip design experienceispreferred.

  • Exposure to DFT is preferred.

  • Proficiencyin writing Linux shell scripts in Perl, TCL, and Python.

  • Real chiptapeoutexperiencein7nm and/or below with a successful signofftrack record.

  • Self-motivated with strong problem-solving and debugging skills.

  • Ability to work effectively in a dynamic group environment.

What We Can Offer You:

Health & Wellbeing

We strive to provide our team members and their loved ones with a comprehensive suite of benefits that supports their physical, financial and emotional wellbeing.

Personal & Professional Development

We also invest in your career because the better you are, the better we all are. We have specific programs catered to helping you reach any career goals you have - whether you want to become a knowledge expert in your field or apply your skills to another division.

Unconditional Inclusion

We are unconditionally inclusive in the way we work and celebrate individual uniqueness. We know varied backgrounds are valued and succeed here. We have the flexibility to manage our work and personal needs. We make bold moves, together, and are a force for good.

Let's Stay Connected:

Follow @HPECareers on Instagram to see the latest on people, culture and tech at HPE.

#unitedstates

Job:

Engineering

Job Level:

TCP_03"The expected salary/wage range for this position is provided below. Actual offer may vary from this range based upon geographic location, work experience, education/training, and/or skill level.
- United States of America: Annual Salary USD 120,000 - 243,000 in California
The listed salary range reflects base salary. Variable incentives may also be offered."

Information about employee benefits offered in the US can be found at https://myhperewards.com/main/new-hire-enrollment.html

HPE is an Equal Employment Opportunity/ Veterans/Disabled/LGBT employer. We do not discriminate on the basis of race, gender, or any other protected category, and all decisions we make are made on the basis of qualifications, merit, and business need. Our goal is to be one global team that is representative of our customers, in an inclusive environment where we can continue to innovate and grow together. Please click here: Equal Employment Opportunity.

Hewlett Packard Enterprise is EEO Protected Veteran/ Individual with Disabilities.

HPE will comply with all applicable laws related to employer use of arrest and conviction records, including laws requiring employers to consider for employment qualified applicants with criminal histories.

Recruitment Fraud Alert

We have become aware of an increase in fraudulent recruitment activities in which individuals impersonate our company or authorized recruitment agencies to offer fake employment opportunities. These scams may occur through false websites, emails, social media, or chat-based applications and often aim to obtain personal information or money. Please note that Hewlett Packard Enterprise (HPE), its direct and indirect subsidiaries and affiliated companies, and its authorized recruitment agencies/vendors will never charge a candidate a registration fee, hiring fee, or any other fee in connection with its recruitment and hiring process. We also never request personal information such as back account details, Social Security numbers, or national IDs via social media or chat applications.

All legitimate job opportunities will come through official company channels, and candidates are responsible for verifying the credentials of any third party claiming to represent the company. Any reliance on fraudulent communication is at the individual's own risk, and HPE disclaims legal liability for any resulting damages. If you suspect recruitment fraud, do not share personal information or make any payments and report the incident to your local authorities immediately.

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