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Asic Physical Design Engineer Jobs (NOW HIRING)

Physical Design Engineer

Bodega Bay, CA · On-site

$180K - $230K/yr

We're looking for a hands-on Physical Design Engineer to support complex SoC projects for our ... Profile of preferred candidate includes 10 + years of hands-on experience, custom ASIC, strong ...

Physical Design Engineer

Bodega Bay, CA

$161K - $166K/yr

We're looking for a hands-on Physical Design Engineer to support complex SoC projects for our ... Profile of preferred candidate includes 10 + years of hands-on experience, custom ASIC, strong ...

Your Impact As a Physical Design Engineer, you will play a key role in the full RTL-to-GDSII ... Bachelor's degree in Electrical or Computer engineering and 7+ years of ASIC relevant experience ...

Physical Design Engineer

Milpitas, CA · On-site

$195K - $220K/yr

Physical Design Engineer - Socionext America, Milpitas Description Socionext Inc. (SNI) is an ... Critical to this position is the ability to articulate technical discussions with ASIC Customers ...

As an ASIC Engineer focused on Physical Design, you will drive the physical implementation of custom ASICs from floorplanning through tapeout, working across a full-custom silicon design flow. In ...

Your Impact As a Physical Design Engineer, you will play a key role in the full RTL-to-GDSII ... Bachelor's degree in Electrical or Computer engineering and 7+ years of ASIC relevant experience ...

As an ASIC Engineer focused on Physical Design, you will drive the physical implementation of custom ASICs from floorplanning through tapeout, working across a full-custom silicon design flow. In ...

Your Impact As a Physical Design Engineer, you will play a key role in the full RTL-to-GDSII ... Bachelor's degree in Electrical or Computer engineering and 7+ years of ASIC relevant experience ...

ASIC/SOC CAD Engineer

Mountain View, CA · On-site +1

$175K - $362K/yr

MatX is seeking a Physical Design CAD Engineer to join our team as we create best-in-class silicon for high-performance and sustainable GenAI. The ASIC/SOC Physically Design CAD Engineer will be ...

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Asic Physical Design Engineer information

See salary details

$95K

$141.5K

How much do asic physical design engineer jobs pay per year?

As of Jul 14, 2026, the average yearly pay for asic physical design engineer in the United States is $139,408.00, according to ZipRecruiter salary data. Most workers in this role earn between $136,000.00 and $140,000.00 per year, depending on experience, location, and employer.

What are the key skills and qualifications needed to thrive in the Asic Physical Design Engineer position, and why are they important?

As an ASIC Physical Design Engineer, you need strong expertise in digital design, timing analysis, and semiconductor technology, often supported by a degree in electrical or computer engineering. Familiarity with EDA tools like Cadence, Synopsys, and Mentor Graphics for place-and-route, as well as relevant certifications in VLSI design, are highly valuable. Attention to detail, effective communication, and problem-solving abilities distinguish top professionals in this field. These competencies are crucial for ensuring accurate, efficient, and manufacturable ASIC designs in a fast-paced technological environment.

What are the typical daily responsibilities of an ASIC Physical Design Engineer?

As an ASIC Physical Design Engineer, your daily tasks often include translating RTL designs into physical layouts, performing place-and-route, running static timing analysis, and optimizing power, performance, and area metrics. You will frequently collaborate with design, verification, and fabrication teams to address design challenges and ensure seamless integration of IP blocks. Regular project meetings, documentation of design processes, and participation in design reviews are also common. This role involves balancing technical precision with teamwork, making communication skills and adaptability essential for success.

What is an ASIC Physical Design Engineer job?

An ASIC Physical Design Engineer is responsible for the back-end design and implementation of integrated circuits (ICs). They handle tasks such as floorplanning, placement, routing, timing closure, power optimization, and Design for Manufacturability (DFM). Using Electronic Design Automation (EDA) tools, they ensure the IC meets performance, power, and area (PPA) requirements. They collaborate with front-end design, verification, and fabrication teams to ensure a successful chip tape-out.

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What cities are hiring for Asic Physical Design Engineer jobs? Cities with the most Asic Physical Design Engineer job openings:
What are the most commonly searched types of Asic Physical Design Engineer jobs? The most popular types of Asic Physical Design Engineer jobs are:
What states have the most Asic Physical Design Engineer jobs? States with the most job openings for Asic Physical Design Engineer jobs include:
Sr. SOC/ASIC Physical Design Engineer (Silicon Engineering)

Sr. SOC/ASIC Physical Design Engineer (Silicon Engineering)

SpaceX

Sunnyvale, CA

$175K - $280K/yr

Other

Medical, Dental, Vision, Life, Retirement, PTO

Re-posted 18 days ago


SpaceX rating

8.8

Company rating: 8.8 out of 10

Based on 146 frontline employees who took The Breakroom Quiz

7th of 61 rated aerospace companies


Job description

SR. SOC/ASIC PHYSICAL DESIGN ENGINEER (SILICON ENGINEERING)

At SpaceX we're leveraging our experience in building rockets and spacecraft to deploy Starlink, the world's most advanced broadband internet system. Starlink is the world's largest satellite constellation and is providing fast, reliable internet to millions of users worldwide. We design, build, test, and operate all parts of the system - thousands of satellites, consumer receivers that allow users to connect within minutes of unboxing, and the software that brings it all together. We've only begun to scratch the surface of Starlink's potential global impact and are looking for best-in-class engineers to help maximize Starlink's utility for communities and businesses around the globe. 

We are seeking a motivated, proactive, and intellectually curious engineer who will work alongside world-class cross-disciplinary teams (systems, firmware, architecture, design, validation, product engineering, ASIC implementation). In this role, you will be developing cutting-edge next-generation silicon for deployment in space and ground infrastructures around the globe. These chips are enabling connectivity in places it has previously not been available, affordable or reliable. Your efforts will help deliver cutting-edge solutions that will expand the performance and capabilities of the Starlink network.   

RESPONSIBILITIES:

  • Perform partition synthesis and physical implementation steps (e.g. synthesis, floorplanning, power/ground grid generation, place and route, timing, noise, physical verification, electromigration, voltage drop, logic equivalency and other signoff checks)
  • Develop/improve physical design methodologies and automation scripts for various implementation steps
  • Closely collaborate with the ASIC design team to drive architectural feasibility studies, develop timing, power and area design targets, and explore RTL/design tradeoffs
  • Resolve design/timing/congestion and flow issues, identify potential solutions and drive execution
  • Run, debug, and fix signoff closure issues in static timing analysis (STA), noise, logic equivalency, physical verification, electromigration and voltage drop

BASIC QUALIFICATIONS:

  • Bachelor's degree in electrical engineering, computer engineering or computer science
  • 5+ years of ASIC and/or physical design flow development experience in industry

PREFERRED SKILLS AND EXPERIENCE:

  • Strong experience in ASIC/SOC RTL2GDSII physical design and signoff flows
  • Strong experience with industry standard EDA tools including understanding of their capabilities and underlying algorithms
  • Knowledge of deep sub-micron FinFET and CMOS solid state physics
  • Knowledge of CMOS digital design principles, basic standard cells their functionality, standard cell libraries
  • Understanding of CMOS power dissipation in deep submicron processes leakage/dynamic
  • Familiar with CMOS analog circuit and physical design
  • Knowledge of DFT/Scan/MBIST/LBIST and understanding of their impact on physical design flows
  • Good scripting skills (csh/bash, Perl, Python, TCL, Makefile etc.)
  • Self-driven individual with a can-do attitude, willing to learn, and an ability to work in a dynamic group environment

ADDITIONAL REQUIREMENTS:    

  • Ability to work extended hours and weekends as needed to meet critical project milestones   

COMPENSATION AND BENEFITS:

Pay range:    
Physical Design Engineer/Senior: $175,000.00 - $280,000.00/per year    
Your actual level and base salary will be determined on a case-by-case basis and may vary based on the following considerations: job-related knowledge and skills, education, and experience.

Base salary is just one part of your total rewards package at SpaceX. You may also be eligible for long-term incentives, in the form of company stock, stock options, or long-term cash awards, as well as potential discretionary bonuses and the ability to purchase additional stock at a discount through an Employee Stock Purchase Plan. You will also receive access to comprehensive medical, vision, and dental coverage, access to a 401(k) retirement plan, short & long-term disability insurance, life insurance, paid parental leave, and various other discounts and perks. You may also accrue 3 weeks of paid vacation & will be eligible for 10 or more paid holidays per year. Exempt employees are eligible for 5 days of sick leave per year.


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