1

Asic Manager Jobs (NOW HIRING)

Principal ASIC Design Engineer

Boulder, CO ยท On-site

$180 - $220/hr

Reporting to the Hardware Engineering Manager, you'll collaborate closely with a talented group of ... Establish ASIC design processes internal to Atom Computing by defining methodologies across ...

New

The Sr. ASIC EDA Workflow Engineer will lead EDA tool flow management and engineering workflow development, optimizing and improving EDA workflows for ASIC design processes in a fast-paced, agile ...

ASIC Engineer 5 Duties: * Oversees definition, design, verification, and documentation for ASIC ... Drive Power-domains, level-shifting, power-management requirement * Drive DFX requirement ...

ASIC Engineer

Dobbs Ferry, NY ยท On-site

$90 - $130/hr

Specific team norms around working hours will be communicated by your manager. NOTE: By applying to ... As part of a project team you will work alongside Senior ASIC Engineers; supporting the design ...

New

Manage and mentor electrical and computer engineers through knowledge transfer on technical ... ASIC designs * Willing to travel within the Continental United States (CONUS). Preferred ...

Manage and expand relationships with internal and external development partners. * Be a key contributor to ASIC roadmaps and future innovation. * Lead cross-discipline task force to triage product HW ...

Showing results 21-40

Asic Manager information

See salary details

$11

$24

$46

How much do asic manager jobs pay per hour?

As of Aug 7, 2026, the average hourly pay for asic manager in the United States is $24.32, according to ZipRecruiter salary data. Most workers in this role earn between $17.07 and $29.33 per hour, depending on experience, location, and employer.

What are the key skills and qualifications needed to thrive as an ASIC manager?

To thrive as an ASIC Manager, you need deep expertise in digital and analog integrated circuit design, project management experience, and typically a degree in electrical engineering or a related field. Familiarity with EDA tools like Cadence, Synopsys, and Mentor Graphics, as well as knowledge of verification methodologies and relevant industry certifications, is crucial. Strong leadership, problem-solving abilities, and excellent communication skills help in managing cross-functional teams and collaborating with stakeholders. These skills ensure successful delivery of complex ASIC projects, meeting quality, timeline, and budget requirements.

What is an ASIC manager?

An ASIC Manager is a professional responsible for overseeing the design, development, and implementation of Application-Specific Integrated Circuits (ASICs). They coordinate teams of engineers, manage project timelines, and ensure that ASIC projects meet technical and business requirements. ASIC Managers often collaborate with other departments, handle resource allocation, and address technical challenges throughout the development process. Their role is crucial in industries like electronics, telecommunications, and computing, where custom hardware solutions are needed for optimized performance.

What is the difference between Asic Manager vs Asic Engineer?

AspectAsic ManagerAsic Engineer
ResponsibilitiesOversees ASIC design projects, manages teams, coordinates with stakeholdersDesigns, develops, and tests ASIC chips
Required SkillsLeadership, project management, ASIC design knowledgeHardware description languages, circuit design, verification
CertificationsTypically none required, but PMP or management certifications helpfulASIC design certifications or relevant technical training
Work EnvironmentOffice-based, team management, project coordinationDesign labs, engineering teams, hardware development

The main difference between an Asic Manager and an Asic Engineer lies in their roles. The Asic Manager oversees projects and manages teams, focusing on coordination and leadership. In contrast, the Asic Engineer is hands-on, involved in designing and testing ASIC chips. Both roles require technical ASIC knowledge, but the Manager emphasizes leadership and project oversight, while the Engineer concentrates on technical design work.

What are the most common challenges ASIC managers face when leading design teams, and how can they address them?

ASIC Managers often encounter challenges such as balancing project timelines with technical complexities, coordinating cross-functional teams, and ensuring effective communication between design, verification, and testing groups. Managing evolving project requirements while maintaining quality standards can also be demanding. Success in this role typically relies on proactive project management, clear delegation of tasks, and fostering a collaborative team environment. Leveraging agile methodologies and regular check-ins can help address these challenges and keep projects on track.
More about Asic Manager jobs
What cities are hiring for Asic Manager jobs? Cities with the most Asic Manager job openings:
What are the most commonly searched types of Asic jobs? The most popular types of Asic jobs are:
What states have the most Asic Manager jobs? States with the most job openings for Asic Manager jobs include:
What job categories do people searching Asic Manager jobs look for? The top searched job categories for Asic Manager jobs are:
Infographic showing various Asic Manager job openings in the United States as of August 2026, with employment types broken down into 88% Full Time, 11% Part Time, and 1% Contract. Highlights an 85% Physical, 2% Hybrid, and 13% Remote job distribution, with an average salary of $50,590 per year, or $24.3 per hour.

Senior Manager, ASIC Design Engineering

Cornelis Networks, Inc.

Austin, TX โ€ข Remote

Full-time

Medical, Dental, Vision, Life, Retirement, PTO

Re-posted yesterday


Job description

Salary:

At Cornelis were building the future of AI and HPC networking with an AI-first approach to silicon and software development. Were seeking engineers who are energized by working on cutting-edge ASIC design and distributed software systems, and who are motivated to push the boundaries on how AI can transform everything from chip architecture to system performance at scale.


At Cornelis were building the future of AI and HPC networking with an AI-first approach to silicon and software development. Were seeking engineers who are energized by working on cutting-edge ASIC design and distributed software systems, and who are motivated to push the boundaries on how AI can transform everything from chip architecture to system performance at scale.


Cornelis Networks delivers the worlds highest performance scale-out networking solutions for AI and HPC datacenters. Our differentiated architecture seamlessly integrates hardware, software and system level technologies to maximize the efficiency of GPU, CPU and accelerator-based compute clusters at any scale. Our solutions drive breakthroughs in AI & HPC workloads, empowering our customers to push the boundaries of innovation. Backed by top-tier venture capital and strategic investors, we are committed to innovation, performance and scalability - solving the worlds most demanding computational challenges with our next-generation networking solutions.


We are a fast-growing, forward-thinking team of architects, engineers, and business professionals with a proven track record of building successful products and companies. As a global organization, our team spans multiple U.S. states and six countries, and we continue to expand with exceptional talent in onsite, hybrid, and fully remote roles.


Cornelis Networks islooking for aSenior ASIC Design Engineering Managerto lead and grow our RTL design engineering team.Reporting to the VP of ASIC Engineering,with direct exposure toexecutive leadership,this leaderwillmanagea team of talented design engineers anddrivefull-lifecycle development ofCornelisnext-generation, high-performance networking ASICs.The role isaccountable forbuilding and driving RTLimplementationschedules acrossallSoC subsystemsand full-chipmilestones. Successrequiresdeep hands-onexpertisein advanced RTL designimplementation,methodologies,and SoC flows,from microarchitecturedefinitionthroughRTL delivery,tape-outreadiness, andcross-functionalexecutionwith Architecture, DesignVerification, Emulation,andPhysical Design.This leaderwill alsoownheadcount planning,hiring,and organizationalstrategyto build animble, efficient,world-classdesign team.Exposureto AI-based design flowsandmethodologyispreferred.


This role isintendedfor a senior engineering leader who can combine hands-on ASIC RTL designexpertisewith disciplined program execution, cross-functional coordination, andteam buildingat scale.


Key Responsibilities

  • OwnASIC RTL delivery schedules across major milestonesbytracking,monitoring,and reportingprogress against committedplans.
  • Utilize data-driven insights to predictschedulerisks and proactively reallocate human resources to keep the project on track.
  • AlignRTL delivery scheduleswith DV andemulationenablement andmanagefeedbackloopsand dependencies efficiently.
  • Facilitatephysical designhandoffsbyensuringdesign teams provide high-quality RTL and constraintsthatminimize timing-closure iterations. Track physical design feedback anddelivery schedules to support physical designsignoff and tape-out milestones.
  • Leadlong-term headcount planning and organizationaldesignfor the ASIC department.Identifyskill gaps and executeglobal talent acquisition strategiesthat support theproduct roadmap.

MinimumQualifications

  • 15+ years in the semiconductor industry,preferably inhigh performancedesigns on advanced technology nodes,with at least5years in people management
  • B.S. or M.S. in Computer Engineering, Electrical Engineering, or related technical field, or equivalent practical experience
  • Deep understanding of the interaction between Design, Verification, Emulation, and Physical Design teams. You must know "how the work gets done" to manage the people doing it.
  • Proven ability to lead largeengineering organizations through multiple full-cycle ASIC product launchesin a remoteenvironment.Ability to coordinate across multiple projects, manage risks and escalations, and work under tight schedules and budget constraints.
  • Strong technicalexpertisein microarchitecture development, RTL coding (Verilog/SystemVerilog), synthesis, STA/timing closure, physical design, and verification methodologies.
  • Exposuretoone or more industry standards/protocol stacks such as PCIe, Ethernet, UCIe,UALink.
  • Demonstrated ability tooptimizedesigns for PPA (power, performance, area) and to integrate major subsystems (interconnect, I/O, memory).


Preferred Qualifications

  • Exposure to AI based design implementation and verification flows, scripting for automation, milestonetrackingand flow integration
  • Experience building globally distributed ASIC design teams and scaling engineering practicesin a remote environment.


Location:This is a remote position for employees residing within the United States.


We offer a competitive compensation package that includes equity, cash, and incentives, along with health and retirement benefits. Our dynamic, flexible work environment provides the opportunity to collaborate with some of the most influential names in the semiconductor industry.


At Cornelis Networks your base salary is only one component of your comprehensive total rewards package. Your base pay will be determined by factors such as your skills, qualifications, experience, and location relative to the hiring range for the position. Depending on your role, you may also be eligible for performance-based incentives, including an annual bonus or sales incentives.


In addition to your base pay, youll have access to a broad range of benefits, including medical, dental, and vision coverage, as well as disability and life insurance, a dependent care flexible spending account, accidental injury insurance, and pet insurance. We also offer generous paid holidays, 401(k) with company match, and Open Time Off (OTO) for regular full-time exempt employees. Other paid time off benefits include sick time, bonding leave, and pregnancy disability leave.


Cornelis Networks does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. Cornelis Networks is an equal opportunity employer, and all qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity or expression, pregnancy, age, national origin, disability status, genetic information, protected veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants needs under the respective laws throughout all stages of the recruitment and selection process.