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Asic Manager Jobs in Toronto, ON (NOW HIRING)

Amd

ASIC Verification Engineer

Thornhill, ON · Hybrid

This is an ASIC Verification Engineering role within the Security IP Team (SECIP). The role focuses ... management, cryptography, data compression, and high-throughput DMA. THE PERSON: The ideal ...

Amd

Principal ASIC Design Engineer

Thornhill, ON · On-site +1

... that manage and optimize AI-driven data movement, enabling industry-leading performance ... PREFERRED EXPERIENCE * Proven track record of leading significant ASIC or silicon design ...

Tenstorrent

Sr. Engineer, Systems Debug

Toronto, ON · Hybrid

A collaborative teammate who can partner effectively with ASIC design, firmware, software, and ... SerDes, power management, and system validation. * Build and improve debug infrastructure ...

Altera

Manager, Static Timing Analysis (STA)

Toronto, ON

CA$144K - CA$209K/yr

Experience: 10+ years of experience in Static Timing Analysis (STA) for ASIC or FPGA designs. * Leadership: 3+ years of experience managing or leading engineering teams. * Technical Expertise: * Deep ...

Amd

Verification Engineer

Thornhill, ON · Hybrid

Strong understanding of different phases of ASIC and/or full custom chip development is required ... Familiarity with verification management tools as well as understanding of database management ...

Tenstorrent

Sr. Network Engineer

Toronto, ON · Hybrid

CA$100K - CA$500K/yr

Design, deploy, and manage Tenstorrent's global data center network infrastructure supporting AI ... Collaborate with world-class hardware, ASIC, firmware, and software engineers to solve complex ...

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All JobsAsic JobsAsic Manager JobsAsic Manager Jobs in Toronto, ON

Asic Manager information

See Toronto, ON salary details

$23.9K

$111.2K

$202.3K

How much do asic manager jobs pay per year?

As of Sep 5, 2026, the average yearly pay for asic manager in Toronto, ON is $111,174.00, according to ZipRecruiter salary data. Most workers in this role earn between $57,260.00 and $156,988.00 per year, depending on experience, location, and employer.

What is an ASIC manager?

An ASIC Manager is a professional responsible for overseeing the design, development, and implementation of Application-Specific Integrated Circuits (ASICs). They coordinate teams of engineers, manage project timelines, and ensure that ASIC projects meet technical and business requirements. ASIC Managers often collaborate with other departments, handle resource allocation, and address technical challenges throughout the development process. Their role is crucial in industries like electronics, telecommunications, and computing, where custom hardware solutions are needed for optimized performance.

What are the key skills and qualifications needed to thrive as an ASIC manager?

To thrive as an ASIC Manager, you need deep expertise in digital and analog integrated circuit design, project management experience, and typically a degree in electrical engineering or a related field. Familiarity with EDA tools like Cadence, Synopsys, and Mentor Graphics, as well as knowledge of verification methodologies and relevant industry certifications, is crucial. Strong leadership, problem-solving abilities, and excellent communication skills help in managing cross-functional teams and collaborating with stakeholders. These skills ensure successful delivery of complex ASIC projects, meeting quality, timeline, and budget requirements.

What are the most common challenges ASIC managers face when leading design teams, and how can they address them?

ASIC Managers often encounter challenges such as balancing project timelines with technical complexities, coordinating cross-functional teams, and ensuring effective communication between design, verification, and testing groups. Managing evolving project requirements while maintaining quality standards can also be demanding. Success in this role typically relies on proactive project management, clear delegation of tasks, and fostering a collaborative team environment. Leveraging agile methodologies and regular check-ins can help address these challenges and keep projects on track.

What is the difference between Asic Manager vs Asic Engineer?

AspectAsic ManagerAsic Engineer
ResponsibilitiesOversees ASIC design projects, manages teams, coordinates with stakeholdersDesigns, develops, and tests ASIC chips
Required SkillsLeadership, project management, ASIC design knowledgeHardware description languages, circuit design, verification
CertificationsTypically none required, but PMP or management certifications helpfulASIC design certifications or relevant technical training
Work EnvironmentOffice-based, team management, project coordinationDesign labs, engineering teams, hardware development

The main difference between an Asic Manager and an Asic Engineer lies in their roles. The Asic Manager oversees projects and manages teams, focusing on coordination and leadership. In contrast, the Asic Engineer is hands-on, involved in designing and testing ASIC chips. Both roles require technical ASIC knowledge, but the Manager emphasizes leadership and project oversight, while the Engineer concentrates on technical design work.

Asic Manager jobs near you
Infographic showing various Asic Manager job openings in Toronto, ON as of June 2026, with employment types broken down into 99% Full Time, and 1% Contract. Highlights an 88% Physical, 8% Hybrid, and 4% Remote job distribution, with an average salary of $111,174 per year, or $53.4 per hour.

Sr. Principal Program Manager, ASIC Design

Astera Labs

Toronto, ON • On-site

Full-time

Re-posted 12 days ago

Key responsibilities

  • Own the cross-functional execution framework for advanced ASIC programs from early planning through tapeout.

  • Drive milestones, dependencies, execution reviews, decision-making forums, risk management, and tapeout readiness across multiple engineering teams.

  • Partner with various teams and external partners to ensure cross-functional alignment, manage dependencies, and track program progress.

Job description

Role Overview

As a Sr. Principal Program Manager, ASIC Design at Astera Labs, you will own the cross-functional execution framework for advanced ASIC programs from early planning through tapeout. You will drive milestones, dependencies, execution reviews, decision-making forums, risk management, and tapeout readiness across multiple engineering teams.

You will partner closely with architecture, RTL design, functional verification, emulation, DFT, synthesis, physical design, CAD, IP, product management, engineering leadership, and external partners.

This is a high-impact role for a technical program leader who can operate in a fast-moving environment, manage ambiguity, drive accountability, and establish scalable execution practices across complex silicon development programs.

Key Responsibilities

  • Program Execution & Planning

    • Lead pre-silicon execution of complex ASIC and subsystem programs from concept through tapeout.
    • Own program plans, schedules, milestones, dependencies, risk registers, dashboards, and executive-level status reporting.
    • Drive pre-silicon and NPD phase-gate execution from kickoff through final GDS handoff, ensuring cross-functional readiness across architecture, RTL, verification, DFT, physical design, signoff, and tapeout.

  • Cross-Functional Alignment & Coordination

    • Drive cross-functional alignment across architecture, RTL design, verification, emulation, DFT, synthesis, physical design, CAD, IP integration, product management, and external partners.
    • Track IP delivery, PDK updates, CAD/EDA flow readiness, tool dependencies, and foundry requirements.
    • Partner with Post-Silicon PM and Validation teams to absorb feedback from post silicon bring up, including bug reports and Si issues.

  • Risk Management & Decision-Making

    • Identify execution risks, lead risk mitigation plans, and drive trade-off decisions across scope, schedule, resources, and quality.
    • Communicate program health, risks, dependencies, and decisions clearly to engineering teams, senior leaders, executives, and external partners.

  • Process & Operational Excellence

    • Establish scalable program management practices, operating rhythms, decision forums, documentation standards, and communication mechanisms, lead constant improvement.

Basic Qualifications

  • Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related technical field.
  • 10+ years of experience in ASIC/SoC development or silicon program execution, including 3+ years in technical program management, engineering program management, or technical leadership.
  • Experience managing pre-silicon ASIC development flows, including architecture planning, RTL design, functional verification, synthesis, DFT, physical design, timing closure, signoff, and tapeout.
  • Experience with advanced process nodes and high-performance ASIC/SoC development.
  • Strong understanding of ASIC development milestones from product requirements through final GDS handoff.
  • Familiarity with EDA flows, CAD infrastructure, IP integration, PDK readiness, foundry requirements, and vendor dependency management.
  • Experience with pre-silicon validation platforms such as simulation, emulation, FPGA prototyping, or hardware/software co-validation.
  • Experience driving complex cross-functional programs with multiple engineering teams, technical dependencies, external vendors, and aggressive schedules.

Preferred Qualifications

  • Strong technical judgment with the ability to manage trade-offs across performance, power, area, cost, schedule, quality, and risk.
  • Excellent communication, organizational, leadership, and stakeholder-management skills.
  • Ability to influence without authority across global, cross-functional, and cross-cultural teams.
  • Ability to operate independently in a fast-paced, ambiguous, high-growth environment.
  • Experience with high-speed connectivity, SerDes, PHY, PCIe, CXL, Ethernet, networking, switching, or AI infrastructure silicon.

Salary range is CAD 195,000 to CAD 240,000 depending on experience, level, and business need. This role may be eligible for discretionary bonus, incentives and benefits.

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