$200K - $280K/yr
The Role We are seeking a Principal ASIC Package Design Engineer to lead advanced ASIC package ... management for power-dense ASICs. * Fluent in SI/PI and EM simulation tools such as SIWave, HFSS ...
OR · On-site
$180K - $260K/yr
The Role We are seeking a Senior ASIC Package Design Engineer to implement advanced ASIC package ... management for power-dense ASICs. * Fluent in SI/PI and EM simulation tools such as SIWave, HFSS ...
Senior ASIC (Front-End) Design Engineer
OR · Remote
$200K - $300K/yr
Senior ASIC Front-End Design Engineer Summary: * As a Senior ASIC Front-End Design Engineer, you ... management, and software interfaces. * You will be a trusted self-starter who can work with very ...
Senior ASIC (Front-End) Design Engineer
OR · Remote
$200K - $300K/yr
Senior ASIC Front-End Design Engineer Summary: * As a Senior ASIC Front-End Design Engineer, you ... management, and software interfaces. * You will be a trusted self-starter who can work with very ...
We are now looking for a Senior Verification Engineer for our Memory Management Unit. NVIDIA is seeking outstanding ASIC Verification Engineer to verify the world's leading GPUs. This position offers ...
We are now looking for a Senior Verification Engineer for our Memory Management Unit. NVIDIA is seeking outstanding ASIC Verification Engineer to verify the world's leading GPUs. This position offers ...
OR · On-site
$170K - $250K/yr
Manage regression testing, simulation farms, and CI pipelines to ensure high test throughput and ... Participate in ASIC team interviews. * Contribute to advancement of DV methodologies and ...
Sr. Digital ASIC Engineer
Hillsboro, OR · On-site
$91K - $177K/yr
... of management, and the freedom to make meaningful contributions in a setting that encourages ... Understanding of ASIC design flow (RTL design, Verficiation, Synthesis, Timing Analysis, Power ...
Sr. Digital ASIC Engineer
Hillsboro, OR · On-site
$91K - $177K/yr
... of management, and the freedom to make meaningful contributions in a setting that encourages ... Understanding of ASIC design flow (RTL design, Verficiation, Synthesis, Timing Analysis, Power ...
$170K - $250K/yr
Manage regression testing, simulation farms, and CI pipelines to ensure high test throughput and ... Participate in ASIC team interviews. * Contribute to advancement of DV methodologies and ...
We are now looking for a Verification Engineer for our Memory Management Unit. NVIDIA is seeking outstanding ASIC Verification Engineer to verify the world's leading GPUs. This position offers the ...
We are now looking for a Verification Engineer for our Memory Management Unit. NVIDIA is seeking outstanding ASIC Verification Engineer to verify the world's leading GPUs. This position offers the ...
Sr. Digital ASIC Engineer
Hillsboro, OR · On-site
$91K - $177K/yr
... of management, and the freedom to make meaningful contributions in a setting that encourages ... Understanding of ASIC design flow (RTL design, Verficiation, Synthesis, Timing Analysis, Power ...
Sr. Digital ASIC Engineer
Hillsboro, OR · On-site
$91K - $177K/yr
... of management, and the freedom to make meaningful contributions in a setting that encourages ... Understanding of ASIC design flow (RTL design, Verficiation, Synthesis, Timing Analysis, Power ...
$170K - $250K/yr
The Role We are seeking a Senior ASIC Physical Design Engineer to help implement advanced SoCs that ... Familiarity with physical design service vendor management or offshore collaboration. * Experience ...
ASIC Design Engineer
Beaverton, OR · On-site
Description As an ASIC Design Engineer, your responsibilities span various aspects of SOC design ... management designs desirable. Ability to communicate optimally across all internal groups ...
ASIC Design Engineer
Beaverton, OR · On-site
Description As an ASIC Design Engineer, your responsibilities span various aspects of SOC design ... management designs desirable. Ability to communicate optimally across all internal groups ...
Description As an ASIC Design Engineer, your responsibilities span various aspects of SOC design ... management designs desirable. Ability to communicate optimally across all internal groups ...
Description As an ASIC Design Engineer, your responsibilities span various aspects of SOC design ... management designs desirable. Ability to communicate optimally across all internal groups ...
Description As an ASIC Design Engineer, your responsibilities span various aspects of SOC design ... management designs desirable. Ability to communicate optimally across all internal groups ...
Description As an ASIC Design Engineer, your responsibilities span various aspects of SOC design ... management designs desirable. Ability to communicate optimally across all internal groups ...
ASIC Design Engineer
Beaverton, OR · On-site
Description As an ASIC Design Engineer, your responsibilities span various aspects of SOC design ... management designs desirable. Ability to communicate optimally across all internal groups ...
ASIC Design Engineer
Beaverton, OR · On-site
Description As an ASIC Design Engineer, your responsibilities span various aspects of SOC design ... management designs desirable. Ability to communicate optimally across all internal groups ...
ASIC Physical Design Principal Consultant
$148K - $152K/yr
At least 10 years of experience in VLSI/ASIC Design. * At least 9 years of experience in Netlist ... Experience with project management. * Experience and desire to work in a management consulting ...
ASIC Physical Design Principal Consultant
$148K - $152K/yr
At least 10 years of experience in VLSI/ASIC Design. * At least 9 years of experience in Netlist ... Experience with project management. * Experience and desire to work in a management consulting ...
Position Overview We seek a Senior ASIC Design Engineer to provide technical support to Intel ... Self-driven and results-oriented with ability to manage multiple tasks effectively * Strong ...
Position Overview We seek a Senior ASIC Design Engineer to provide technical support to Intel ... Self-driven and results-oriented with ability to manage multiple tasks effectively * Strong ...
OR · On-site
$130K - $200K/yr
Manage regression testing, simulation farms, and CI pipelines to ensure high test throughput and ... ASIC/SoC verification. * Solid understanding of SystemVerilog, digital logic, and hardware ...
$130K - $200K/yr
Manage regression testing, simulation farms, and CI pipelines to ensure high test throughput and ... ASIC/SoC verification. * Solid understanding of SystemVerilog, digital logic, and hardware ...
$190K - $280K/yr
This role also involves managing external physical design partners, driving tool and flow decisions ... years of experience in ASIC physical design for high-performance SoCs. * Proven end-to-end ...
Senior ASIC Timing Engineer
Hillsboro, OR · Hybrid
We are now looking for a motivated ASIC Timing Engineer to join our dynamic and growing team. If ... generation and management. * Expertise in analysis and fixing of timing paths through ECOs ...
Senior ASIC Timing Engineer
Hillsboro, OR · Hybrid
We are now looking for a motivated ASIC Timing Engineer to join our dynamic and growing team. If ... generation and management. * Expertise in analysis and fixing of timing paths through ECOs ...
Asic Manager information
See Oregon salary details
$12.45 - $15.80
11% of jobs
$17.58 is the 25th percentile. Wages below this are outliers.
$15.80 - $19.15
27% of jobs
The median wage is $21.29 / hr.
$19.15 - $22.50
19% of jobs
$22.50 - $25.85
11% of jobs
$28.68 is the 75th percentile. Wages above this are outliers.
$25.85 - $29.20
9% of jobs
$29.20 - $32.55
9% of jobs
$32.55 - $35.90
5% of jobs
$35.90 - $39.26
4% of jobs
$39.26 - $42.61
4% of jobs
$42.61 - $45.96
1% of jobs
$45.96 - $49.31
0% of jobs
$12
$25
$49
How much do asic manager jobs pay per hour?
As of Jun 26, 2026, the average hourly pay for asic manager in Oregon is $25.72, according to ZipRecruiter salary data. Most workers in this role earn between $18.03 and $31.01 per hour, depending on experience, location, and employer.
What are the key skills and qualifications needed to thrive as an ASIC Manager, and why are they important?
To thrive as an ASIC Manager, you need deep expertise in digital and analog integrated circuit design, project management experience, and typically a degree in electrical engineering or a related field. Familiarity with EDA tools like Cadence, Synopsys, and Mentor Graphics, as well as knowledge of verification methodologies and relevant industry certifications, is crucial. Strong leadership, problem-solving abilities, and excellent communication skills help in managing cross-functional teams and collaborating with stakeholders. These skills ensure successful delivery of complex ASIC projects, meeting quality, timeline, and budget requirements.
What is an ASIC Manager?
An ASIC Manager is a professional responsible for overseeing the design, development, and implementation of Application-Specific Integrated Circuits (ASICs). They coordinate teams of engineers, manage project timelines, and ensure that ASIC projects meet technical and business requirements. ASIC Managers often collaborate with other departments, handle resource allocation, and address technical challenges throughout the development process. Their role is crucial in industries like electronics, telecommunications, and computing, where custom hardware solutions are needed for optimized performance.
What is the difference between Asic Manager vs Asic Engineer?
| Aspect | Asic Manager | Asic Engineer |
|---|---|---|
| Responsibilities | Oversees ASIC design projects, manages teams, coordinates with stakeholders | Designs, develops, and tests ASIC chips |
| Required Skills | Leadership, project management, ASIC design knowledge | Hardware description languages, circuit design, verification |
| Certifications | Typically none required, but PMP or management certifications helpful | ASIC design certifications or relevant technical training |
| Work Environment | Office-based, team management, project coordination | Design labs, engineering teams, hardware development |
The main difference between an Asic Manager and an Asic Engineer lies in their roles. The Asic Manager oversees projects and manages teams, focusing on coordination and leadership. In contrast, the Asic Engineer is hands-on, involved in designing and testing ASIC chips. Both roles require technical ASIC knowledge, but the Manager emphasizes leadership and project oversight, while the Engineer concentrates on technical design work.
What are the most common challenges ASIC Managers face when leading design teams, and how can they address them?
ASIC Managers often encounter challenges such as balancing project timelines with technical complexities, coordinating cross-functional teams, and ensuring effective communication between design, verification, and testing groups. Managing evolving project requirements while maintaining quality standards can also be demanding. Success in this role typically relies on proactive project management, clear delegation of tasks, and fostering a collaborative team environment. Leveraging agile methodologies and regular check-ins can help address these challenges and keep projects on track.
What are popular job titles related to Asic Manager jobs in Oregon? For Asic Manager jobs in Oregon, the most frequently searched job titles are:
What job categories do people searching Asic Manager jobs in Oregon look for? The top searched job categories for Asic Manager jobs in Oregon are:
$200K - $280K/yr
Other
Medical, Dental, Vision, Life, PTO
Posted 13 days ago
Job description
The Role
We are seeking a Principal ASIC Package Design Engineer to lead advanced ASIC package architecture and execution, with a strong focus on flip-chip BGA (FC-BGA) and multi-chip module (MCM) solutions. This role owns the end-to-end package strategy for high-performance mixed-signal and digital SoCs from early architecture and trade studies through vendor engagement, qualification, and production ramp. You will operate as the technical authority for package design, defining standards, influencing silicon and system architecture, and ensuring first-pass success for complex, high-speed, power-dense ASICs.
Responsibilities
- Own ASIC package architecture for FC-BGA and MCM solutions, including substrate stack-up, ball-map strategy, power delivery, signal breakout, and mechanical constraints.
- Lead package-level trade studies across cost, performance, power integrity (PI), signal integrity (SI), thermal, manufacturability, and reliability.
- Define long-term packaging roadmap aligned with future ASIC nodes, bandwidth scaling, and multi-die integration.
- Establish organizational package design standards, methodologies, and best practices.
- Drive detailed design of FC-BGA packages for high-pin-count ASICs with high-speed SerDes, dense power grids, and RF signal content.
- Define and review substrate stack-ups, via strategies, impedance control, escape routing, and reference plane planning.
- Partner with silicon, RF, and systems teams to co-optimize die floorplans and package interfaces.
- Own package-level SI/PI strategy, including high-speed digital interfaces (e.g., SerDes, JESD, Interlaken), power delivery network (PDN) design, and decoupling strategy
- Lead thermal architecture at the package level, including lid selection, TIMs, heat-spreaders, and mechanical interfaces to system cooling.
- Serve as the primary technical interface to substrate vendors, assembly houses, and OSATs.
- Drive material selection, substrate technology choices, and assembly process optimization.
QualificationsÂ
- Bachelor's degree in Packaging Engineering, Mechanical Engineering, Electrical Engineering, or a related field.
- 10+ years of experience in ASIC package design, with deep expertise in FC-BGA.
- Proven experience delivering high-pin-count, high-performance ASIC packages into production.
- Strong understanding of substrate technologies and materials, SI/PI fundamentals at the package level, and thermal management for power-dense ASICs.
- Fluent in SI/PI and EM simulation tools such as SIWave, HFSS, and ADS.
- Experience working directly with OSATs and substrate vendors.
- Knowledge of packaging qualification and test methodologies.
Nice to Have
- Experience with MCM or heterogeneous integration (chiplets, interposers, advanced laminates).
- Background in high-speed digital or mixed-signal SoCs.
- Familiarity with aerospace, space, or high-reliability electronics.
- Experience defining packaging strategy from early architecture through first silicon and volume ramp.
- Demonstrated history of building or scaling package design methodology within an organization.
Compensation and Benefits:
- Base salary range for this role is $200,000 - $280,000 + equity in the company
- Salary will be based on several factors including, but not limited to: knowledge and skills, education, and experience level
- Comprehensive benefits package including paid time off, medical/dental/vision/ coverage, life insurance, paid parental leave, and many other perks
About K2 Space
Sourced by ZipRecruiter
Industry
Guided missile and space vehicle manufacturing
Company size
11 - 50 Employees
Headquarters location
Los Angeles, CA, US
Year founded
2022