OR · On-site
$170K - $250K/yr
The Role We are seeking a Senior ASIC Emulation Engineer who will lead the bring-up, deployment ... Manage interactions with external IP providers or emulation partners when needed. Qualifications
We are now looking for a Senior Verification Engineer for our Memory Management Unit. NVIDIA is seeking outstanding ASIC Verification Engineer to verify the world's leading GPUs. This position offers ...
We are now looking for a Senior Verification Engineer for our Memory Management Unit. NVIDIA is seeking outstanding ASIC Verification Engineer to verify the world's leading GPUs. This position offers ...
$190K - $285K/yr
Manage regression testing, simulation farms, and CI pipelines to ensure high test throughput and ... Participate in ASIC team interviews. * Drive advancement of DV methodologies and improvements.
OR · On-site
$170K - $250K/yr
Manage regression testing, simulation farms, and CI pipelines to ensure high test throughput and ... Participate in ASIC team interviews. * Contribute to advancement of DV methodologies and ...
... management system with complex build requirements. Our approach delivers the performance required ... Come, join our GPU ASIC team and help build the real-time, cost-effective computing platform ...
... management system with complex build requirements. Our approach delivers the performance required ... Come, join our GPU ASIC team and help build the real-time, cost-effective computing platform ...
We are now looking for a Verification Engineer for our Memory Management Unit. NVIDIA is seeking outstanding ASIC Verification Engineer to verify the world's leading GPUs. This position offers the ...
We are now looking for a Verification Engineer for our Memory Management Unit. NVIDIA is seeking outstanding ASIC Verification Engineer to verify the world's leading GPUs. This position offers the ...
Proven success managing long-cycle, highly technical, multi-stakeholder sales pursuits. * Strong ... ASIC sales roles typically require strong technical semiconductor knowledge. * Extensive network ...
Proven success managing long-cycle, highly technical, multi-stakeholder sales pursuits. * Strong ... ASIC sales roles typically require strong technical semiconductor knowledge. * Extensive network ...
ASIC Design Engineer
Beaverton, OR · On-site
Description As an ASIC Design Engineer, your responsibilities span various aspects of SOC design ... management designs desirable. Ability to communicate optimally across all internal groups ...
ASIC Design Engineer
Beaverton, OR · On-site
Description As an ASIC Design Engineer, your responsibilities span various aspects of SOC design ... management designs desirable. Ability to communicate optimally across all internal groups ...
Description As an ASIC Design Engineer, your responsibilities span various aspects of SOC design ... management designs desirable. Ability to communicate optimally across all internal groups ...
Description As an ASIC Design Engineer, your responsibilities span various aspects of SOC design ... management designs desirable. Ability to communicate optimally across all internal groups ...
$170K - $250K/yr
The Role We are seeking a Senior ASIC Physical Design Engineer to help implement advanced SoCs that ... Familiarity with physical design service vendor management or offshore collaboration. * Experience ...
ASIC Physical Design Principal Consultant
Hillsboro, OR · On-site
$148K - $152K/yr
At least 10 years of experience in VLSI/ASIC Design. * At least 9 years of experience in Netlist ... Experience with project management. * Experience and desire to work in a management consulting ...
ASIC Physical Design Principal Consultant
Hillsboro, OR · On-site
$148K - $152K/yr
At least 10 years of experience in VLSI/ASIC Design. * At least 9 years of experience in Netlist ... Experience with project management. * Experience and desire to work in a management consulting ...
Position Overview We seek a Senior ASIC Design Engineer to provide technical support to Intel ... Self-driven and results-oriented with ability to manage multiple tasks effectively * Strong ...
Position Overview We seek a Senior ASIC Design Engineer to provide technical support to Intel ... Self-driven and results-oriented with ability to manage multiple tasks effectively * Strong ...
We are now looking for a motivated ASIC Timing Engineer to join our dynamic and growing team. If ... generation and management. * Expertise in analysis and fixing of timing paths through ECOs ...
We are now looking for a motivated ASIC Timing Engineer to join our dynamic and growing team. If ... generation and management. * Expertise in analysis and fixing of timing paths through ECOs ...
OR · On-site
$190K - $280K/yr
This role also involves managing external physical design partners, driving tool and flow decisions ... years of experience in ASIC physical design for high-performance SoCs. * Proven end-to-end ...
FPGA Engineering Manager (Nextest, Tualatin, OR)
Tualatin, OR · On-site
$171 - $273.60/hr
FPGA Engineering Manager (Memory Test, Tualatin, OR) Date: Jul 13, 2026 Location: Tualatin, OR, US ... Minimum of 5 years of experience as an FPGA/ASIC project lead, driving multiple projects through ...
FPGA Engineering Manager (Nextest, Tualatin, OR)
Tualatin, OR · On-site
$171 - $273.60/hr
FPGA Engineering Manager (Memory Test, Tualatin, OR) Date: Jul 13, 2026 Location: Tualatin, OR, US ... Minimum of 5 years of experience as an FPGA/ASIC project lead, driving multiple projects through ...
FPGA Engineering Manager (MTD, Tualatin, OR)
Tualatin, OR · On-site
$155K - $248K/yr
Minimum of 5 years of experience as an FPGA/ASIC project lead, driving multiple projects through ... Experience as a first level manager of an engineering team. * Experience with FPGA Transceiver ...
FPGA Engineering Manager (MTD, Tualatin, OR)
Tualatin, OR · On-site
$155K - $248K/yr
Minimum of 5 years of experience as an FPGA/ASIC project lead, driving multiple projects through ... Experience as a first level manager of an engineering team. * Experience with FPGA Transceiver ...
FPGA Engineering Manager (MTD, Tualatin, OR)
Tualatin, OR · On-site
$155K - $248K/yr
Minimum of 5 years of experience as an FPGA/ASIC project lead, driving multiple projects through ... Experience as a first level manager of an engineering team. * Experience with FPGA Transceiver ...
FPGA Engineering Manager (MTD, Tualatin, OR)
Tualatin, OR · On-site
$155K - $248K/yr
Minimum of 5 years of experience as an FPGA/ASIC project lead, driving multiple projects through ... Experience as a first level manager of an engineering team. * Experience with FPGA Transceiver ...
Description As an ASIC STA Engineer, you will have responsibilities spanning all aspects of SoC ... constraints generation and management, proficient in scripting languages (Tcl and Perl ...
Description As an ASIC STA Engineer, you will have responsibilities spanning all aspects of SoC ... constraints generation and management, proficient in scripting languages (Tcl and Perl ...
Timing Design Engineer
Beaverton, OR · On-site
Description As an ASIC STA Engineer, you will have responsibilities spanning all aspects of SoC ... Hands on experience in timing/SDC constraints generation and management. Proficient in scripting ...
Timing Design Engineer
Beaverton, OR · On-site
Description As an ASIC STA Engineer, you will have responsibilities spanning all aspects of SoC ... Hands on experience in timing/SDC constraints generation and management. Proficient in scripting ...
Description As an ASIC STA Engineer, you will have responsibilities spanning all aspects of SoC ... Hands on experience in timing/SDC constraints generation and management. Proficient in scripting ...
Description As an ASIC STA Engineer, you will have responsibilities spanning all aspects of SoC ... Hands on experience in timing/SDC constraints generation and management. Proficient in scripting ...
Asic Manager information
See Oregon salary details
$12.45 - $15.80
11% of jobs
$17.58 is the 25th percentile. Wages below this are outliers.
$15.80 - $19.15
27% of jobs
The median wage is $21.29 / hr.
$19.15 - $22.50
19% of jobs
$22.50 - $25.85
11% of jobs
$28.68 is the 75th percentile. Wages above this are outliers.
$25.85 - $29.20
9% of jobs
$29.20 - $32.55
9% of jobs
$32.55 - $35.90
5% of jobs
$35.90 - $39.26
4% of jobs
$39.26 - $42.61
4% of jobs
$42.61 - $45.96
1% of jobs
$45.96 - $49.31
0% of jobs
$12
$25
$49
How much do asic manager jobs pay per hour?
As of Aug 7, 2026, the average hourly pay for asic manager in Oregon is $25.72, according to ZipRecruiter salary data. Most workers in this role earn between $18.03 and $31.01 per hour, depending on experience, location, and employer.
What are the key skills and qualifications needed to thrive as an ASIC manager?
To thrive as an ASIC Manager, you need deep expertise in digital and analog integrated circuit design, project management experience, and typically a degree in electrical engineering or a related field. Familiarity with EDA tools like Cadence, Synopsys, and Mentor Graphics, as well as knowledge of verification methodologies and relevant industry certifications, is crucial. Strong leadership, problem-solving abilities, and excellent communication skills help in managing cross-functional teams and collaborating with stakeholders. These skills ensure successful delivery of complex ASIC projects, meeting quality, timeline, and budget requirements.
What is an ASIC manager?
An ASIC Manager is a professional responsible for overseeing the design, development, and implementation of Application-Specific Integrated Circuits (ASICs). They coordinate teams of engineers, manage project timelines, and ensure that ASIC projects meet technical and business requirements. ASIC Managers often collaborate with other departments, handle resource allocation, and address technical challenges throughout the development process. Their role is crucial in industries like electronics, telecommunications, and computing, where custom hardware solutions are needed for optimized performance.
What is the difference between Asic Manager vs Asic Engineer?
| Aspect | Asic Manager | Asic Engineer |
|---|---|---|
| Responsibilities | Oversees ASIC design projects, manages teams, coordinates with stakeholders | Designs, develops, and tests ASIC chips |
| Required Skills | Leadership, project management, ASIC design knowledge | Hardware description languages, circuit design, verification |
| Certifications | Typically none required, but PMP or management certifications helpful | ASIC design certifications or relevant technical training |
| Work Environment | Office-based, team management, project coordination | Design labs, engineering teams, hardware development |
The main difference between an Asic Manager and an Asic Engineer lies in their roles. The Asic Manager oversees projects and manages teams, focusing on coordination and leadership. In contrast, the Asic Engineer is hands-on, involved in designing and testing ASIC chips. Both roles require technical ASIC knowledge, but the Manager emphasizes leadership and project oversight, while the Engineer concentrates on technical design work.
What are the most common challenges ASIC managers face when leading design teams, and how can they address them?
ASIC Managers often encounter challenges such as balancing project timelines with technical complexities, coordinating cross-functional teams, and ensuring effective communication between design, verification, and testing groups. Managing evolving project requirements while maintaining quality standards can also be demanding. Success in this role typically relies on proactive project management, clear delegation of tasks, and fostering a collaborative team environment. Leveraging agile methodologies and regular check-ins can help address these challenges and keep projects on track.
What are popular job titles related to Asic Manager jobs in Oregon? For Asic Manager jobs in Oregon, the most frequently searched job titles are:
What job categories do people searching Asic Manager jobs in Oregon look for? The top searched job categories for Asic Manager jobs in Oregon are:
$170K - $250K/yr
Full-time
Medical, Dental, Vision, Life, PTO
Posted 4 days ago
Job description
The Role
We are seeking a Senior ASIC Emulation Engineer who will lead the bring-up, deployment, and optimization of our pre-silicon emulation platforms. You will work closely with architecture, RTL design, DFT, DV, firmware, physical design, and silicon validation teams to enable highfidelity hardware/software co-development and accelerate verification cycles. This is a hands-on role with high ownership, deep technical engagement, and the opportunity to shape firstgeneration silicon and system methodology.
Responsibilities
- Build, integrate, and maintain full-chip, multi-chips and system-level emulation models on platforms such as Palladium, ZeBu, or Veloce.
- Define and evolve emulation strategy, methodology, and workflows across the ASIC organization.
- Work with RTL engineers to compile, map, and optimize designs for emulation performance, capacity, and stability.
- Develop and integrate transactors, BFMs, speed adapters, and virtualization interfaces to support diverse system use cases.
- Support systemlevel testing in emulation by enabling full hardware/software integration, validating complex use cases, and ensuring the environment can run representative endtoend workloads.
- Accelerate overall verification throughput by helping DV team run targeted and highvalue tests in emulation, including adapting DV content and optimizing flows to reduce simulation bottlenecks.
- Enable firmware, bootloader, driver, and software teams by providing robust emulation platforms and assisting in HW/SW integration debug.
- Run emulation workloads, triage failures, perform root-cause analysis, and collaborate across design and verification to resolve issues.
- Maintain and enhance automation for compile flows, regression management, and continuous integration.
- Participate in architecture reviews, microarchitecture discussions, and influence design-for-emulation best practices.
- Support silicon bring-up and post-silicon validation through test reuse, diagnostics, and pre/post-silicon correlation.
- Manage interactions with external IP providers or emulation partners when needed.
Qualifications
- B.S. or M.S. in Electrical Engineering, Computer Engineering, or related field.
- 5+ years of experience in ASIC/SoC development, focused on emulation
- Solid understanding of SystemVerilog, digital logic, RTL flows, DV methodologies, and ASIC development lifecycles.
- Hands-on expertise with major emulation platforms (Palladium, ZeBu, Veloce), including model build, debug and performance optimization
- Proficiency with scripting languages (Python, Perl, TCL) for automation and tooling.
- Experience with hardware/software interfaces, embedded processors, firmware bring-up, and C/C++based system-level testing.
- Familiarity with industry-standard buses and protocols such as APB/AHB/AXI, JTAG, SPI.
- Experience driving cross-functional debug involving RTL, DV, firmware, physical design, and validation teams.
- Understanding of pre- and post-silicon debug methodologies and correlation workflows.
Nice to Have
- Experience with FPGA prototyping platforms (HAPS, Protium, custom FPGA boards).
- Experience with low-power modes and power-aware emulation.
- Experience with analog/mixed-signal behavioral models in emulation environments.
- Experience with SERDES and high-speed data protocols such as PCIe, Ethernet, USB, or multi-gigabit PHYs.
Compensation and Benefits:
- Base salary range for this role is $170,000 - $250,000 + equity in the company
- Salary will be based on several factors including, but not limited to: knowledge and skills, education, and experience level
- Comprehensive benefits package including paid time off, medical/dental/vision/ coverage, life insurance, paid parental leave, and many other perks
About K2 Space
Sourced by ZipRecruiter
Industry
Guided missile and space vehicle manufacturing
Company size
11 - 50 Employees
Headquarters location
Los Angeles, CA, US
Year founded
2022