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Asic Manager Jobs in Oregon (NOW HIRING)

Intel

EDA Tools SW Engineer

Hillsboro, OR · Hybrid

$173K - $330K/yr

... ASIC tools/flows and Physical verification/runsets, Tape-in Verification and IP sign off for test ... Technical management or lead experience mentoring or leading medium sized teams. * Experience with ...

Sonsoft Inc

SoC Design and Verification

Hillsboro, OR

$148K - $180K/yr

Knowledge of ASIC design methodologies and flows * Ability to Manage and conduct training for the team * Worked with companies and seen at least a couple of tape-outs * Project management ...

Intel

Director, SoC Design Engineering

Hillsboro, OR

$148K - $180K/yr

... management experience - Expertise in SystemVerilog and UVM/OVM verification methodologies ... Product Enablement (IP, tools, and methodologies), Custom ASIC (leveraging existing IP for custom ...

Rambus

SPE Hardware Architecture

Hillsboro, OR · On-site

$189K - $352K/yr

Work closely with product management, product marketing, technical field organization and customers ... Knowledge of front-end ASIC development flow and best practices * Knowledge of system architecture ...

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Asic Manager information

See Oregon salary details

$12

$25

$49

How much do asic manager jobs pay per hour?

As of Aug 8, 2026, the average hourly pay for asic manager in Oregon is $25.72, according to ZipRecruiter salary data. Most workers in this role earn between $18.03 and $31.01 per hour, depending on experience, location, and employer.

What are the key skills and qualifications needed to thrive as an ASIC manager?

To thrive as an ASIC Manager, you need deep expertise in digital and analog integrated circuit design, project management experience, and typically a degree in electrical engineering or a related field. Familiarity with EDA tools like Cadence, Synopsys, and Mentor Graphics, as well as knowledge of verification methodologies and relevant industry certifications, is crucial. Strong leadership, problem-solving abilities, and excellent communication skills help in managing cross-functional teams and collaborating with stakeholders. These skills ensure successful delivery of complex ASIC projects, meeting quality, timeline, and budget requirements.

What is an ASIC manager?

An ASIC Manager is a professional responsible for overseeing the design, development, and implementation of Application-Specific Integrated Circuits (ASICs). They coordinate teams of engineers, manage project timelines, and ensure that ASIC projects meet technical and business requirements. ASIC Managers often collaborate with other departments, handle resource allocation, and address technical challenges throughout the development process. Their role is crucial in industries like electronics, telecommunications, and computing, where custom hardware solutions are needed for optimized performance.

What is the difference between Asic Manager vs Asic Engineer?

AspectAsic ManagerAsic Engineer
ResponsibilitiesOversees ASIC design projects, manages teams, coordinates with stakeholdersDesigns, develops, and tests ASIC chips
Required SkillsLeadership, project management, ASIC design knowledgeHardware description languages, circuit design, verification
CertificationsTypically none required, but PMP or management certifications helpfulASIC design certifications or relevant technical training
Work EnvironmentOffice-based, team management, project coordinationDesign labs, engineering teams, hardware development

The main difference between an Asic Manager and an Asic Engineer lies in their roles. The Asic Manager oversees projects and manages teams, focusing on coordination and leadership. In contrast, the Asic Engineer is hands-on, involved in designing and testing ASIC chips. Both roles require technical ASIC knowledge, but the Manager emphasizes leadership and project oversight, while the Engineer concentrates on technical design work.

What are the most common challenges ASIC managers face when leading design teams, and how can they address them?

ASIC Managers often encounter challenges such as balancing project timelines with technical complexities, coordinating cross-functional teams, and ensuring effective communication between design, verification, and testing groups. Managing evolving project requirements while maintaining quality standards can also be demanding. Success in this role typically relies on proactive project management, clear delegation of tasks, and fostering a collaborative team environment. Leveraging agile methodologies and regular check-ins can help address these challenges and keep projects on track.
What are popular job titles related to Asic Manager jobs in Oregon? For Asic Manager jobs in Oregon, the most frequently searched job titles are:
What job categories do people searching Asic Manager jobs in Oregon look for? The top searched job categories for Asic Manager jobs in Oregon are:
Asic Manager jobs near you
Infographic showing various Asic Manager job openings in Oregon as of August 2026, with employment types broken down into 88% Full Time, 11% Part Time, and 1% Contract. Highlights an 84% Physical, 3% Hybrid, and 13% Remote job distribution, with an average salary of $53,488 per year, or $25.7 per hour.

EDA Tools SW Engineer

Intel

Hillsboro, OR • Hybrid

$173K - $330K/yr

Full-time

Medical, Retirement, PTO

Posted 4 days ago

Intel rating

8.7

Company rating: 8.7 out of 10

Based on 147 frontline employees who took The Breakroom Quiz

19th of 156 rated electronics manufacturers

Job description

Job Details:Job Description: 

At Intel, Design Technology Platforms (DTP) is one of the key pillars enabling Intel to deliver winning products in the marketplace. You will directly drive and work with DTP cross teams to ensure design-kits leadership for customer enablement for cutting edge technologies. You will work with customers to outline critical requirements, collaborate with Intel internal partners to define the scope, plan execution, innovate competitive solutions to meet customer needs.
The Technical Lead position within the Design Enablement (DTP) organization of Intel Foundry is a Design Enablement Applications and Support Technical Lead position chartered to lead a team that drives customer solutions for ASIC tools/flows and Physical verification/runsets, Tape-in Verification and IP sign off for test chips when customers use Intel PDK collaterals in these domains. The job requires partnering and leveraging domain experts across various areas of Technology Development, EDA vendors and product design teams (internal to Intel and external) to deliver quality solutions.
Lead and develop a high-performing engineering team by setting priorities, driving execution across organizational boundaries, and fostering an inclusive and collaborative work environment. Provide technical leadership, mentoring, and coaching while ensuring delivery of engineering objectives aligned with schedule, quality, and cost targets.

Direct and coordinate engineering activities, allocate resources effectively, and drive problem resolution through sound technical judgment. Promote team values, accountability, and continuous improvement while guiding employee development, performance, and productivity. Exercise independent judgment in addressing complex challenges that may require deviation from standard practices.

Required behavior traits

  • Strong customer focus with a commitment to responsive support and issue resolution.

  • Demonstrated analytical problem-solving skills and ability to collaborate across organizations.

  • Proven leadership, influencing, and communication skills, with experience driving results through cross-functional teams.

Qualifications:

You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the requirements and are considered a plus factor in identifying top candidates.
Minimum Qualifications:

  • BS degree with 10+ years of experience or MS degree with 8+ years of experience or PhD degree with 6+ years of experience in Electrical Engineer or Computer Engineering or related field.

6+ years of experience in two or more of the following:

  • Technical management or lead experience mentoring or leading medium sized teams.

  • Experience with Test chip physical verification and tape-in

  • Intel and/or external foundry process technology knowledge in advance nodes.

  • Industry direct experience and in-depth knowledge to support customers in ASIC/Physical Design and/or Physical Verification/runsets, in advanced technology nodes, or EDA tools.

  • Experience with technology challenges, and process changes that impact the Physical Design, Physical Verification and other PDK components.

Preferred Qualifications

  • Experience in advanced-node semiconductor design and verification methodologies.

  • Experience with customers and stakeholders to resolve complex design and technology challenges.

Job Type:Experienced HireShift:Shift 1 (United States of America)Primary Location: US, Oregon, HillsboroAdditional Locations:US, Arizona, Phoenix, US, California, Santa Clara, US, Texas, AustinPosting Statement:All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.Position of TrustN/ABenefits

We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel.

Annual Salary Range for jobs which could be performed in the US: $173,660.00-330,340.00 USDThe range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.

Work Model for this Role

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.

*

ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.

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About Intel

Sourced by ZipRecruiter

Intel strives to make every facet of semiconductor manufacturing state-of-the-art -- from semiconductor process development and manufacturing, through yield improvement to packaging, final test and optimization, and world class Supply Chain and facilities support. Employees in the Technology and Manufacturing Group are part of a worldwide network of design, development, manufacturing, and assembly/test facilities, all focused on utilizing the power of Moore's Law to bring smart, connected devices to every person on Earth

Industry

Manufacturing

Company size

10,000+ Employees

Headquarters location

Santa Clara, CA, US

Year founded

1968

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