The Sr. ASIC EDA Workflow Engineer will lead EDA tool flow management and engineering workflow development, optimizing and improving EDA workflows for ASIC design processes in a fast-paced, agile ...
The Sr. ASIC EDA Workflow Engineer will lead EDA tool flow management and engineering workflow development, optimizing and improving EDA workflows for ASIC design processes in a fast-paced, agile ...
Lead ASIC DFT engineer.
San Jose, CA · On-site
$194K/yr
Role: Lead ASIC DFT Engineer Location: San Jose, CA Work Setup: Remote however once/month in office. PST time zone preferred Designation: Associate Experience Required: * 10+ years of hands-on ...
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Lead ASIC DFT engineer.
San Jose, CA · On-site
$194K/yr
Role: Lead ASIC DFT Engineer Location: San Jose, CA Work Setup: Remote however once/month in office. PST time zone preferred Designation: Associate Experience Required: * 10+ years of hands-on ...
Sr. Engineer, ASIC Design
San Jose, CA · On-site
$160K - $192K/yr
Engineer, ASIC Design Location: San Jose (on-site) Ayar Labs is shattering AI data bottlenecks by moving data at the speed of light. As pioneers of co-packaged optics (CPO), we are using light ...
Sr. Engineer, ASIC Design
San Jose, CA · On-site
$160K - $192K/yr
Engineer, ASIC Design Location: San Jose (on-site) Ayar Labs is shattering AI data bottlenecks by moving data at the speed of light. As pioneers of co-packaged optics (CPO), we are using light ...
OR · Hybrid
In the role of a Senior LPU ASIC Engineer, you will play a crucial role in our innovative LPU chip design. * Full-Flow Ownership: Responsible for Synthesis, floorplanning, place & route, timing ...
ASIC Engineer 4
$195K - $247K/yr
... ASIC Engineer-related occupation. Position also requires experience in: 1. IC Place and Route 2. Static timing analysis 3. Chip floor planning 4. Custom flow support (Tcl based) 5. Cadence tools:
ASIC Engineer 4
$195K - $247K/yr
... ASIC Engineer-related occupation. Position also requires experience in: 1. IC Place and Route 2. Static timing analysis 3. Chip floor planning 4. Custom flow support (Tcl based) 5. Cadence tools:
ASIC Test Engineer
San Jose, CA · On-site
$194K/yr
ASIC Test Engineer ASIC Test Engineer for industrialization of new products Imec imec is the world-leading research and innovation hub in nanoelectronics and digital technologies. The combination of ...
ASIC Test Engineer
San Jose, CA · On-site
$194K/yr
ASIC Test Engineer ASIC Test Engineer for industrialization of new products Imec imec is the world-leading research and innovation hub in nanoelectronics and digital technologies. The combination of ...
ASIC Test Engineer
San Jose, CA · On-site
$194K/yr
ASIC Test Engineer ASIC Test Engineer for industrialization of new products Imec imec is the world-leading research and innovation hub in nanoelectronics and digital technologies. The combination of ...
ASIC Test Engineer
San Jose, CA · On-site
$194K/yr
ASIC Test Engineer ASIC Test Engineer for industrialization of new products Imec imec is the world-leading research and innovation hub in nanoelectronics and digital technologies. The combination of ...
Lead ASIC DFT Engineer - Remote
San Jose, CA · On-site +1
$192K/yr
Lead ASIC DFT Engineer Location: San Jose, CA Work Setup: Remote, PST time zone preferred Contract Term: Contract Experience Required: * 10+ years of hands-on experience in ASIC Design-for-Test (DFT ...
Lead ASIC DFT Engineer - Remote
San Jose, CA · On-site +1
$192K/yr
Lead ASIC DFT Engineer Location: San Jose, CA Work Setup: Remote, PST time zone preferred Contract Term: Contract Experience Required: * 10+ years of hands-on experience in ASIC Design-for-Test (DFT ...
In the role of a Senior LPU ASIC Engineer, you will play a crucial role in our innovative LPU chip design. * Full-Flow Ownership: Responsible for Synthesis, floorplanning, place & route, timing ...
In the role of a Senior LPU ASIC Engineer, you will play a crucial role in our innovative LPU chip design. * Full-Flow Ownership: Responsible for Synthesis, floorplanning, place & route, timing ...
This is a hands-on role that's ideal for ASIC EDA experts who have a multi-disciplinary engineering/DevOps background, along with a keen interest in generative AI, and a passion for designing ...
This is a hands-on role that's ideal for ASIC EDA experts who have a multi-disciplinary engineering/DevOps background, along with a keen interest in generative AI, and a passion for designing ...
May perform the duties of a project engineer. * Recommend new tools and practices for continuous improvement in the group's ASIC/FPGA design flow. * Provide guidance or mentor other engineers with a ...
May perform the duties of a project engineer. * Recommend new tools and practices for continuous improvement in the group's ASIC/FPGA design flow. * Provide guidance or mentor other engineers with a ...
ASIC Engineer 4
Minneapolis, MN · On-site
$195K - $247K/yr
... ASIC Engineer-related occupation. Position also requires experience in: 1. IC Place and Route 2. Static timing analysis 3. Chip floor planning 4. Custom flow support (Tcl based) 5. Cadence tools:
ASIC Engineer 4
Minneapolis, MN · On-site
$195K - $247K/yr
... ASIC Engineer-related occupation. Position also requires experience in: 1. IC Place and Route 2. Static timing analysis 3. Chip floor planning 4. Custom flow support (Tcl based) 5. Cadence tools:
Come work at Amazon! We're hiring an ASIC Engineer within a high performance ASIC design team. This team is using industry leading methodologies to develop proprietary IP's. The Role: Be part of Leo ...
Come work at Amazon! We're hiring an ASIC Engineer within a high performance ASIC design team. This team is using industry leading methodologies to develop proprietary IP's. The Role: Be part of Leo ...
Lead ASIC DFT Engineer
San Jose, CA · On-site
$194K/yr
Lead ASIC DFT Engineer Location: San Jose, CA - Onsite Type: Contract Experience 10+ years of hands-on experience in ASIC Design-for-Test (DFT) Required Skills & Qualifications * Strong hands-on ...
Lead ASIC DFT Engineer
San Jose, CA · On-site
$194K/yr
Lead ASIC DFT Engineer Location: San Jose, CA - Onsite Type: Contract Experience 10+ years of hands-on experience in ASIC Design-for-Test (DFT) Required Skills & Qualifications * Strong hands-on ...
Principal ASIC Engineer
San Jose, CA · On-site
$233K - $336K/yr
... Engineer-related occupation. Position requires: 1. Perl, Python, PCIE, NVME, UVM, and System Verilog. 2. ASIC simulation tools and verification methods. 3. Defining verification architecture ...
Principal ASIC Engineer
San Jose, CA · On-site
$233K - $336K/yr
... Engineer-related occupation. Position requires: 1. Perl, Python, PCIE, NVME, UVM, and System Verilog. 2. ASIC simulation tools and verification methods. 3. Defining verification architecture ...
May perform the duties of a project engineer. * Recommend new tools and practices for continuous improvement in the group's ASIC/FPGA design flow. * Provide guidance or mentor other engineers with a ...
May perform the duties of a project engineer. * Recommend new tools and practices for continuous improvement in the group's ASIC/FPGA design flow. * Provide guidance or mentor other engineers with a ...
Sr. ASIC EDA Workflow Engineer
Sunnyvale, CA · On-site +1
This is a hands-on role that's ideal for ASIC EDA experts who have a multi-disciplinary engineering/DevOps background, along with a keen interest in generative AI, and a passion for designing ...
Sr. ASIC EDA Workflow Engineer
Sunnyvale, CA · On-site +1
This is a hands-on role that's ideal for ASIC EDA experts who have a multi-disciplinary engineering/DevOps background, along with a keen interest in generative AI, and a passion for designing ...
Come work at Amazon! We're hiring an ASIC Engineer within a high performance ASIC design team. This team is using industry leading methodologies to develop proprietary IP's. The Role: Be part of Leo ...
Come work at Amazon! We're hiring an ASIC Engineer within a high performance ASIC design team. This team is using industry leading methodologies to develop proprietary IP's. The Role: Be part of Leo ...
Principal ASIC Engineer
$233K - $336K/yr
... Engineer-related occupation. Position requires: 1. Perl, Python, PCIE, NVME, UVM, and System Verilog. 2. ASIC simulation tools and verification methods. 3. Defining verification architecture ...
Principal ASIC Engineer
$233K - $336K/yr
... Engineer-related occupation. Position requires: 1. Perl, Python, PCIE, NVME, UVM, and System Verilog. 2. ASIC simulation tools and verification methods. 3. Defining verification architecture ...
Principal FPGA/ASIC Engineer - Level 3
$79K - $118K/yr
The Principal FPGA/ASIC Engineer will be responsible for research, requirements analysis and systems architecture, design, coding, test bench design, verification, synthesis and place & route for our ...
Principal FPGA/ASIC Engineer - Level 3
$79K - $118K/yr
The Principal FPGA/ASIC Engineer will be responsible for research, requirements analysis and systems architecture, design, coding, test bench design, verification, synthesis and place & route for our ...
Asic Engineer information
See salary details
$82.5K - $90.2K
4% of jobs
$90.2K - $98K
4% of jobs
$98K - $105.7K
0% of jobs
$105.7K - $113.4K
0% of jobs
$113.4K - $121.1K
0% of jobs
$121.1K - $128.9K
0% of jobs
$128.9K - $136.6K
4% of jobs
$136.6K - $144.3K
2% of jobs
$144.3K - $152K
0% of jobs
$152K - $159.8K
0% of jobs
$160.7K is the 25th percentile. Wages below this are outliers.
$159.8K - $167.5K
85% of jobs
$82.5K
$158.2K
$167.5K
How much do asic engineer jobs pay per year?
As of Jun 9, 2026, the average yearly pay for asic engineer in the United States is $158,244.00, according to ZipRecruiter salary data. Most workers in this role earn between $166,000.00 and $166,000.00 per year, depending on experience, location, and employer.
What Is an ASIC Engineer?
An ASIC Engineer works with the design and verification of an Application-Specific Integrated Circuit (ASIC). This type of integrated circuit is designed for a specified purpose, like digital voice recording or cryptocurrency mining. An ASIC engineer has experience and skills that they use to program the integrated circuit based on defined requirements. They are capable of designing and producing ASICs that have over 100 million logic gates.
What are some typical challenges faced by ASIC Engineers during the design and verification process?
ASIC Engineers often face challenges such as meeting tight performance, power, and area constraints while ensuring design correctness. Debugging complex issues during simulation and post-silicon validation can be time-consuming and require strong problem-solving skills. Additionally, coordinating with cross-functional teams—such as software, hardware, and verification engineers—is crucial to resolve integration issues and keep projects on schedule. Staying updated with evolving EDA tools and industry standards is also important for success in this role.
What are ASIC engineers?
ASIC engineers are professionals who design and develop Application-Specific Integrated Circuits (ASICs), which are customized microchips built for a particular use or product rather than general-purpose use. Their work involves creating circuit designs, verifying and simulating chip functions, and collaborating with other engineers to ensure the chip meets performance, power, and area requirements. ASIC engineers play a crucial role in industries like telecommunications, consumer electronics, automotive, and more, enabling devices to perform specialized tasks efficiently.
What is the difference between Asic Engineer vs FPGA Engineer?
| Aspect | Asic Engineer | FPGA Engineer |
|---|---|---|
| Credentials | Bachelor's or Master's in Electrical Engineering, VLSI Design, or related fields; certifications like IEEE or VLSI certifications | Bachelor's or Master's in Electrical Engineering, Digital Design, or related fields; similar certifications |
| Work Environment | Designing and developing custom integrated circuits in labs or design centers | Implementing and testing FPGA designs in labs or development environments |
| Industry Usage | Used in semiconductor companies, electronics manufacturers, and high-performance computing | Common in prototyping, testing, and flexible hardware solutions across industries |
While both roles involve digital design and hardware development, Asic Engineers focus on creating custom chips for mass production, whereas FPGA Engineers work on programmable hardware for testing and rapid prototyping. The skills and certifications overlap, but their work environments and end goals differ significantly.
What are the key skills and qualifications needed to thrive as an ASIC Engineer, and why are they important?
To thrive as an ASIC Engineer, you need a solid background in digital design, hardware description languages (HDLs) like Verilog or VHDL, and a relevant degree in electrical engineering or a related field. Familiarity with electronic design automation (EDA) tools, simulation software, and knowledge of the ASIC design flow are typically required, with certifications in hardware design being advantageous. Strong problem-solving abilities, attention to detail, and effective communication skills help set top performers apart. These skills are essential for delivering reliable, efficient chip designs while collaborating with cross-functional teams and meeting project specifications.
More about Asic Engineer jobs
What cities are hiring for Asic Engineer jobs? Cities with the most Asic Engineer job openings:
What are the most commonly searched types of Asic Engineer jobs? The most popular types of Asic Engineer jobs are:
Who are the top companies hiring for Asic Engineer jobs? The top employers for Asic Engineer jobs are:
What states have the most Asic Engineer jobs? States with the most job openings for Asic Engineer jobs include:
What job categories do people searching Asic Engineer jobs look for? The top searched job categories for Asic Engineer jobs are:
What are popular job titles related to Asic Engineer jobs? For Asic Engineer jobs, the most frequently searched job titles are:
Full-time
Posted 15 days ago
Job description
Job Summary:
Tensordyne is an AI system solution company that builds high-performance generative AI inference systems. The Sr. ASIC EDA Workflow Engineer will lead EDA tool flow management and engineering workflow development, optimizing and improving EDA workflows for ASIC design processes in a fast-paced, agile environment.
Responsibilities:
• Lead EDA tool flow management, and associated engineering workflow development for multimodal generative AI inference acceleration products.
• Guide and assist colleagues to improve and invent EDA workflows within a fast-paced, agile HPC development environment.
• Drive optimization, implementation and exploration of new EDA tools and technologies for the full ASIC chip design process.
• Continuously innovate and improve scalable, reliable, high-performance systems and tools to enable the next generation of products.
• Work closely with ASIC team members engaged in the design and verification of products to understand and improve their workflows and EDA needs.
Qualifications:
Required:
• Experience leading the development and support for compilation, build automation, testing, packaging and installation project generators that build object files like either CMake, GNU make, and/or Ninja, as well as experience with CI/CD and modern Git Branching workflows.
• Hands-on ASIC engineering experience, that includes knowledge of VLSI/SoC chip design and verification workflows, with ASIC EDA tool suites from Synopsys and/or Cadence.
• Knowledge of Linux system administration and familiarity with cloud-based devops, with experience in supporting EDA tools.
• Programming and debugging skills with key languages to automate tasks and improve efficiency using scripts.
• Prior work experience with supporting ASIC engineers with EDA workflows, including installation of new tool versions, FlexLM license management, and debugging/fixing issues with EDA vendors.
• Excellent analytical, written, and verbal interpersonal skills along with an ability to productively collaborate within a global engineering team that moves at a startup pace.
• Bachelor’s or Master's degree in Computer Science, Computer Engineering, Electrical Engineering or a related technical field.
Company:
Tensordyne is a technology company involved in building AI math, chips, hardware, and software in order to make AI affordable and efficient. Founded in 2017, the company is headquartered in Sunnyvale, USA, with a team of 51-200 employees. The company is currently Growth Stage.
Tensordyne is an AI system solution company that builds high-performance generative AI inference systems. The Sr. ASIC EDA Workflow Engineer will lead EDA tool flow management and engineering workflow development, optimizing and improving EDA workflows for ASIC design processes in a fast-paced, agile environment.
Responsibilities:
• Lead EDA tool flow management, and associated engineering workflow development for multimodal generative AI inference acceleration products.
• Guide and assist colleagues to improve and invent EDA workflows within a fast-paced, agile HPC development environment.
• Drive optimization, implementation and exploration of new EDA tools and technologies for the full ASIC chip design process.
• Continuously innovate and improve scalable, reliable, high-performance systems and tools to enable the next generation of products.
• Work closely with ASIC team members engaged in the design and verification of products to understand and improve their workflows and EDA needs.
Qualifications:
Required:
• Experience leading the development and support for compilation, build automation, testing, packaging and installation project generators that build object files like either CMake, GNU make, and/or Ninja, as well as experience with CI/CD and modern Git Branching workflows.
• Hands-on ASIC engineering experience, that includes knowledge of VLSI/SoC chip design and verification workflows, with ASIC EDA tool suites from Synopsys and/or Cadence.
• Knowledge of Linux system administration and familiarity with cloud-based devops, with experience in supporting EDA tools.
• Programming and debugging skills with key languages to automate tasks and improve efficiency using scripts.
• Prior work experience with supporting ASIC engineers with EDA workflows, including installation of new tool versions, FlexLM license management, and debugging/fixing issues with EDA vendors.
• Excellent analytical, written, and verbal interpersonal skills along with an ability to productively collaborate within a global engineering team that moves at a startup pace.
• Bachelor’s or Master's degree in Computer Science, Computer Engineering, Electrical Engineering or a related technical field.
Company:
Tensordyne is a technology company involved in building AI math, chips, hardware, and software in order to make AI affordable and efficient. Founded in 2017, the company is headquartered in Sunnyvale, USA, with a team of 51-200 employees. The company is currently Growth Stage.