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Asic Development Engineer Jobs in Oregon (NOW HIRING)

Nvidia

OR · Hybrid

$104.40K - $143.40K/yr

As a Senior Formal Verification Engineer at NVIDIA, you will verify ASICs developed at the ... Verify AI-related sophisticated ASIC designs & features with formal verification methods. * Multi ...

Nvidia

OR · Hybrid

... development of sophisticated, detailed layout of IC substrates for NVIDIA products. In addition ... Perform substrate breakout patterns for ASIC packages. * Optimize package pinout incorporating ...

Nvidia

OR · Hybrid

... development of sophisticated, detailed layout of IC substrates for NVIDIA products. In addition ... Perform substrate breakout patterns for ASIC packages. * Optimize package pinout incorporating ...

Apple

Circuits Physical Design Engineer

Beaverton, OR · On-site

$141.50K - $145.70K/yr

As part of our Digital Design Engineering group, you'll take imaginative and revolutionary ideas ... development of block/partitions for silicon validation of foundation Ips.Familiar with ASIC ...

Nvidia

OR · On-site

$119.40K - $157.80K/yr

Core Development: Build, architect, develop, and debug critical firmware running in the GPU OOBHUB ... Collaborate closely with hardware architects and ASIC designers to initiate new silicon, defining ...

Apple

Circuits Physical Design Engineer

Beaverton, OR · On-site

$141.80K - $258.60K/yr

As part of our Digital Design Engineering group, you'll take imaginative and revolutionary ideas ... development of block/partitions for silicon validation of foundation Ips. Familiar with ASIC ...

Apple

Circuits Physical Design Engineer

Beaverton, OR

$141.80K - $258.60K/yr

As part of our Digital Design Engineering group, you'll take imaginative and revolutionary ideas ... development of block/partitions for silicon validation of foundation Ips. Familiar with ASIC ...

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Asic Development Engineer information

What is the difference between Asic Development Engineer vs FPGA Design Engineer?

AspectAsic Development EngineerFPGA Design Engineer
Required CredentialsBachelor's or Master's in Electrical Engineering, VLSI, or related fields; knowledge of ASIC design toolsBachelor's or Master's in Electrical Engineering, Digital Design; familiarity with FPGA development tools
Work EnvironmentDesigning and verifying custom silicon chips in semiconductor labs or R&D centersDeveloping and testing FPGA-based solutions in hardware labs or embedded systems environments
Industry UsageUsed in semiconductor companies, integrated circuit design firms, and tech giantsCommon in telecommunications, aerospace, and embedded systems industries

While both roles involve digital hardware design, Asic Development Engineers focus on creating custom chips for high-performance applications, whereas FPGA Design Engineers work on programmable hardware solutions. Both require strong digital design skills and familiarity with hardware description languages, but their end products and development environments differ.

What are popular job titles related to Asic Development Engineer jobs in Oregon? For Asic Development Engineer jobs in Oregon, the most frequently searched job titles are:
What job categories do people searching Asic Development Engineer jobs in Oregon look for? The top searched job categories for Asic Development Engineer jobs in Oregon are:
Asic Development Engineer jobs near you
Design Engineer - AI SoC Development

Design Engineer - AI SoC Development

Intel

Hillsboro, OR

Full-time

Medical, Retirement, PTO

Posted 19 days ago

Intel rating

8.8

Company rating: 8.8 out of 10

Based on 143 frontline employees who took The Breakroom Quiz

9th of 137 rated electronics manufacturers

Job description

Job Details:Job Description: 

Join Intel's AI RevolutionIntel's AI SoC organization develops cutting-edge products powering a wide range of AI applications, from edge devices to data center accelerators. If you are an engineer with strong technical and communication skills who thrives in a fast-paced environment with abundant learning opportunities, you are the ideal candidate for this role. Join us to shape the future of AI hardware.

What You'll DoAs an RTL Design Engineer, you'll develop logic design, register transfer level (RTL) coding, and simulation for SoC designs, integrating IP blocks and subsystems into full chip SoC or discrete component designs. You'll participate in defining architecture and microarchitecture features while performing quality checks across various logic design aspects from RTL to timing/power convergence.

You'll apply strategies, tools, and methods to write RTL and optimize logic to meet power, performance, area, and timing goals while ensuring design integrity for physical implementation. Working closely with verification teams, you'll review verification plans and resolve failing RTL tests to ensure feature correctness. You'll follow secure development practices and collaborate with IP providers for SoC-level integration and validation.

Key Responsibilities

Architecture & Design Contribute to evaluation of architectural trade-offs considering features, performance, and system constraints Implement RTL in Verilog/System Verilog based on defined micro-architecture Integrate IP blocks at top level and ensure synthesis- and timing-clean design

Verification & Validation Work closely with verification teams to achieve full coverage and robust validation Develop timing constraints for IP blocks and assist physical design teams with synthesis, timing closure, and formal equivalence checks Support silicon bring-up and post-silicon validation activities, including debug and performance analysis

Collaboration & Quality Collaborate with senior engineers to adopt best practices and improve design methodologies Drive quality assurance compliance for smooth IP/SoC handoff Work with IP providers to integrate and validate IPs at the SoC level

Qualifications:

Minimum qualifications are required to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.

Minimum Qualifications Bachelor's degree in Electrical Engineering, Computer Engineering, or Computer Science

4+ years of experience in/with:

  • RTL design and implementation for ASIC/SoC development
  • Proficiency in Verilog/System Verilog for RTL coding and design
  • Experience with synthesis tools and timing closure methodologies

Preferred Qualifications

  • Understanding of clock domain crossings, power optimization, and timing closure
  • Exposure to SoC system integration and CPU subsystem design
  • Familiarity with standard bus protocols (AXI, AHB, etc.) and embedded processor architectures
  • Knowledge of high-speed and low-power design techniques
  • Experience with static timing analysis (STA) tools and methodologies
  • Hands-on experience with formal verification tools and techniques
  • Basic scripting skills (Python, TCL, etc.) for automation
  • Experience with EDA tools: HDL simulators (VCS, Questa, IES), lint tools (Spyglass), and FPGA prototyping tools
  • Ability to work in a dynamic environment and adapt to changing requirements

Strong problem-solving skills, collaborative mindset, and eagerness to learn

Job Type:Experienced HireShift:Shift 1 (United States of America)Primary Location: US, California, FolsomAdditional Locations:US, California, Santa Clara, US, Oregon, Hillsboro, US, Texas, AustinBusiness group:Intel makes possible the most amazing experiences of the future. You may know us for our processors. But we do so much more. Intel invents at the boundaries of technology to make amazing experiences possible for business and society, and for every person on Earth. Harnessing the capability of the cloud, the ubiquity of the Internet of Things, the latest advances in memory and programmable solutions, and the promise of always-on 5G connectivity, Intel is disrupting industries and solving global challenges. Leading on policy, diversity, inclusion, education and sustainability, we create value for our stockholders, customers, and society.Posting Statement:All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.Position of TrustN/ABenefits

We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel.

Annual Salary Range for jobs which could be performed in the US: $164,470.00-232,190.00 USDThe range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.

Work Model for this Role

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.

*

ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.

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About Intel

Sourced by ZipRecruiter

Intel strives to make every facet of semiconductor manufacturing state-of-the-art -- from semiconductor process development and manufacturing, through yield improvement to packaging, final test and optimization, and world class Supply Chain and facilities support. Employees in the Technology and Manufacturing Group are part of a worldwide network of design, development, manufacturing, and assembly/test facilities, all focused on utilizing the power of Moore's Law to bring smart, connected devices to every person on Earth

Industry

Manufacturing

Company size

10,000+ Employees

Headquarters location

Santa Clara, CA, US

Year founded

1968

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