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Asic Development Engineer Jobs in Oregon (NOW HIRING)

K2 Space

OR · On-site

$170K - $250K/yr

Contribute to methodology development, tool evaluation, and flow documentation. * Support your ... Computer Engineering, or related field. * 5-10 years of experience in ASIC physical design for ...

K2 Space

OR · On-site

$170K - $250K/yr

Contribute to methodology development, tool evaluation, and flow documentation. * Support your ... Computer Engineering, or related field. * 5-10 years of experience in ASIC physical design for ...

K2 Space

OR

$130K - $200K/yr

The Role We are seeking an ASIC Design Verification Engineer whose role will be to verify the ... Experience with test planning, testbench development, constrained-random testing, and coverage ...

K2 Space

OR

$160K - $220K/yr

... ASIC, mixedsignal, RF, verification, and system engineering teams. You will help implement core ... Participate in presilicon firmware development and validation activities. * Support postsilicon ...

Nvidia

Senior ASIC Timing Engineer

Hillsboro, OR · Hybrid

We are now looking for a motivated ASIC Timing Engineer to join our dynamic and growing team. If ... Experience in methodology and/or flow development as well as automation. NVIDIA is widely ...

Apple

Timing Design Engineer

Beaverton, OR

... As an ASIC STA Engineer, you will have responsibilities spanning all aspects of SoC design in terms of timing. Key responsibilities include timing sign-off, STA and sign-off flow development ...

Apple

Timing Design Engineer

Beaverton, OR · On-site

... As an ASIC STA Engineer, you will have responsibilities spanning all aspects of SoC design in terms of timing. Key responsibilities include timing sign-off, STA and sign-off flow development ...

Intel

DFT Application Engineer

Hillsboro, OR · On-site

Drive quality improvements in ASIC DFT/DFM and ATPG validation methodology, capability/flow, and ... Professional development in DFT methodologies and foundry services * Direct impact on national ...

Apple

Timing Design Engineer

Beaverton, OR

... As an ASIC STA Engineer, you will have responsibilities spanning all aspects of SoC design in terms of timing. Key responsibilities include timing sign-off, STA and sign-off flow development ...

Apple

Timing Design Engineer

Beaverton, OR · On-site

... As an ASIC STA Engineer, you will have responsibilities spanning all aspects of SoC design in terms of timing. Key responsibilities include timing sign-off, STA and sign-off flow development ...

Altera

Senior Design Verification Engineer

Hillsboro, OR · On-site

$169K - $240K/yr

... ASIC, FPGA, or SoC development; OR Master's degree and 8+ years of experience ; OR PhD and **6+ ... Experience verifying FPGA architecture components, programmable fabric, interconnects, memory ...

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Asic Development Engineer information

What engineer makes $500,000 a year?

An experienced ASIC Development Engineer working in high-demand sectors such as semiconductor design or advanced chip development can earn $500,000 or more annually, especially with seniority, specialized skills, and in competitive markets. Compensation often includes base salary, bonuses, and stock options, particularly in large tech or semiconductor companies.

What is the difference between Asic Development Engineer vs FPGA Design Engineer?

AspectAsic Development EngineerFPGA Design Engineer
Required CredentialsBachelor's or Master's in Electrical Engineering, VLSI, or related fields; knowledge of ASIC design toolsBachelor's or Master's in Electrical Engineering, Digital Design; familiarity with FPGA development tools
Work EnvironmentDesigning and verifying custom silicon chips in semiconductor labs or R&D centersDeveloping and testing FPGA-based solutions in hardware labs or embedded systems environments
Industry UsageUsed in semiconductor companies, integrated circuit design firms, and tech giantsCommon in telecommunications, aerospace, and embedded systems industries

While both roles involve digital hardware design, Asic Development Engineers focus on creating custom chips for high-performance applications, whereas FPGA Design Engineers work on programmable hardware solutions. Both require strong digital design skills and familiarity with hardware description languages, but their end products and development environments differ.

What engineers make $300,000 a year?

Senior engineers in high-demand fields such as software engineering, data engineering, and ASIC development can earn $300,000 or more annually, especially with extensive experience, specialized skills, and working in competitive industries or companies. Roles like senior hardware or ASIC design engineers often reach this level with advanced technical expertise and leadership responsibilities.

Are ASIC engineers in demand?

ASIC development engineers are in high demand due to the growth of industries like consumer electronics, telecommunications, and automotive systems that require custom integrated circuits. Skills in hardware description languages such as VHDL or Verilog, along with experience in FPGA prototyping and verification, enhance employability in this field.

How much do ASIC engineers make?

ASIC development engineers typically earn between $80,000 and $150,000 annually, depending on experience, location, and company size. Senior engineers with specialized skills in hardware description languages and verification tools can earn higher salaries, often exceeding $150,000.
What are popular job titles related to Asic Development Engineer jobs in Oregon? For Asic Development Engineer jobs in Oregon, the most frequently searched job titles are:
What job categories do people searching Asic Development Engineer jobs in Oregon look for? The top searched job categories for Asic Development Engineer jobs in Oregon are:
Asic Development Engineer jobs near you
Senior ASIC Physical Design Engineer

Senior ASIC Physical Design Engineer

K2 Space

OR • On-site

$170K - $250K/yr

Other

Medical, Dental, Vision, Life, PTO

This job post has expired 1 day ago. Applications are no longer accepted.

Job description

The Role 

We are seeking a Senior ASIC Physical Design Engineer to help implement advanced SoCs that power next-generation satellite and space systems. In this role, you will contribute to the full physical design flow-from synthesis to GDSII-working closely with architecture, RTL, verification, and packaging teams. You'll be a key contributor in achieving timing closure, optimizing PPA, and supporting design integration with external partners. You will be part of a collaborative design team developing state-of-the-art mixed-signal SoCs to be hosted on some of the largest, most powerful, rapidly designed and rapidly manufactured satellites ever deployed in space. In your first 6 months, you will develop and implement new SoC sub-systems for satellite communications and beyond. In your first two years, you will have contributed to developing cutting-edge SoCs that will fly in space. 

Responsibilities 

  • Execute the complete physical design flow for complex SoC blocks and top-level integration, including synthesis, floorplanning, place & route, CTS, STA, and physical verification. 
  • Perform timing closure and optimization across multiple corners and modes using industry-standard tools. 
  • Collaborate with front-end, verification, and DFT teams to ensure clean handoff and predictable convergence. 
  • Work with external physical design service providers and internal leads to review deliverables, resolve issues, and ensure schedule alignment. 
  • Develop and maintain scripts and automation to improve flow efficiency and consistency. 
  • Support physical sign-off activities including DRC/LVS, IR drop, EM, and power analysis. 
  • Assist in chip-level integration, ECOs, and tapeout preparation. 
  • Contribute to methodology development, tool evaluation, and flow documentation. 
  • Support your product through production and spaceflight.  

Required Qualifications 

  • Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or related field. 
  • 5-10 years of experience in ASIC physical design for complex SoCs. 
  • Hands-on experience with industry-standard tools (Synopsys ICC2/Fusion Compiler, Cadence Innovus, or equivalent). 
  • Strong understanding of timing analysis, power optimization, and physical verification flows. 
  • Experience with hierarchical or flat SoC design methodologies. 
  • Familiarity with FinFET technologies. 
  • Working knowledge of DFT, UPF/CPF power intent, and ECO implementation. 
  • Strong problem-solving skills and ability to work cross-functionally in fast-paced environments. 

Preferred Qualifications 

  • Exposure to radiation-hardened or space-qualified ASICs. 
  • Experience with chip-package co-design or advanced packaging (2.5D/3D). 
  • Familiarity with physical design service vendor management or offshore collaboration. 
  • Experience with sign-off through TSMC. 
  • Experience with Gate-All-Around technologies.  
  • Experience working in cross-functional, geographically distributed teams. 

Compensation and Benefits:

  • Base salary range for this role is $170,000 - $250,000 + equity in the company
  • Salary will be based on several factors including, but not limited to: knowledge and skills, education, and experience level
  • Comprehensive benefits package including paid time off, medical/dental/vision/ coverage, life insurance, paid parental leave, and many other perks
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About K2 Space

Sourced by ZipRecruiter

Industry

Guided missile and space vehicle manufacturing

Company size

11 - 50 Employees

Headquarters location

Los Angeles, CA, US

Year founded

2022

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