OR · Hybrid
As an Senior ASIC Power Engineer in our Santa Clara, CA office, you will play a meaningful role in ... Strong fundamentals in digital build flow and Verilog (especially low power RTL development)
OR · Hybrid
As an Senior ASIC Power Engineer in our Santa Clara, CA office, you will play a meaningful role in ... Strong fundamentals in digital build flow and Verilog (especially low power RTL development)
Position Overview We seek a Senior ASIC Design Engineer to provide technical support to Intel ... The team focuses on customer-driven, end-to-end solutions with short development cycles to deliver ...
Position Overview We seek a Senior ASIC Design Engineer to provide technical support to Intel ... The team focuses on customer-driven, end-to-end solutions with short development cycles to deliver ...
This role sits at the intersection of silicon, board design, FPGA/ASIC development, and platform ... Provide technical leadership and mentorship to distributed engineering teams across hardware ...
This role sits at the intersection of silicon, board design, FPGA/ASIC development, and platform ... Provide technical leadership and mentorship to distributed engineering teams across hardware ...
Hillsboro, OR · On-site
$144K/yr
General Information Job Title R&D Engineering, Sr Staff Engineer - 16844 Job ID 16844 City ... Enabling customers to achieve optimal timing, area, and power results in their ASIC and SoC designs.
Hillsboro, OR · On-site
$144K/yr
General Information Job Title R&D Engineering, Sr Staff Engineer - 16844 Job ID 16844 City ... Enabling customers to achieve optimal timing, area, and power results in their ASIC and SoC designs.
Strong financial and business acumen, including investment case development, margin analysis, and ... Bachelor's degree in Electrical Engineering, Computer Engineering, or a related technical field ...
Strong financial and business acumen, including investment case development, margin analysis, and ... Bachelor's degree in Electrical Engineering, Computer Engineering, or a related technical field ...
Beaverton, OR · On-site
Support the design and development of analog ASIC circuits for probe amplifier applications * Contribute to the design of a well-defined functional block under the guidance of senior engineers ...
Beaverton, OR · On-site
Support the design and development of analog ASIC circuits for probe amplifier applications * Contribute to the design of a well-defined functional block under the guidance of senior engineers ...
We are now looking for a motivated ASIC Timing Engineer to join our dynamic and growing team. If ... Experience in methodology and/or flow development as well as automation. NVIDIA is widely ...
We are now looking for a motivated ASIC Timing Engineer to join our dynamic and growing team. If ... Experience in methodology and/or flow development as well as automation. NVIDIA is widely ...
OR · On-site
$190K - $280K/yr
You will own the constraints development and validation-from RTL handoff to synthesis -and ... Computer Engineering, or related field * 10+ years of experience in ASIC design for high ...
$144K - $216K/yr
... best development practices. * Contributing to internal documentation, knowledge sharing, and ... Enabling customers to achieve optimal timing, area, and power results in their ASIC and SoC designs.
$144K - $216K/yr
... best development practices. * Contributing to internal documentation, knowledge sharing, and ... Enabling customers to achieve optimal timing, area, and power results in their ASIC and SoC designs.
... and ASIC/SoC methodology. • Comfortable working in Linux/UNIX development environments. • Excellent debugging, analytical, and problem-solving skills. Company : Synopsys is the leader in ...
... and ASIC/SoC methodology. • Comfortable working in Linux/UNIX development environments. • Excellent debugging, analytical, and problem-solving skills. Company : Synopsys is the leader in ...
Support and deliver ASIC/Digital tool/flow/methodologysolutions using Cadence tool suites to ... Establish andmaintainquality assurance processes for design flow validation Design Flow Development ...
Support and deliver ASIC/Digital tool/flow/methodologysolutions using Cadence tool suites to ... Establish andmaintainquality assurance processes for design flow validation Design Flow Development ...
Beaverton, OR · On-site
As an ASIC STA Engineer, you will have responsibilities spanning all aspects of SoC design in terms of timing. Key responsibilities include timing sign-off, STA and sign-off flow development ...
Beaverton, OR · On-site
As an ASIC STA Engineer, you will have responsibilities spanning all aspects of SoC design in terms of timing. Key responsibilities include timing sign-off, STA and sign-off flow development ...
... As an ASIC STA Engineer, you will have responsibilities spanning all aspects of SoC design in terms of timing. Key responsibilities include timing sign-off, STA and sign-off flow development ...
... As an ASIC STA Engineer, you will have responsibilities spanning all aspects of SoC design in terms of timing. Key responsibilities include timing sign-off, STA and sign-off flow development ...
Hillsboro, OR · On-site
Drive quality improvements in ASIC DFT/DFM and ATPG validation methodology, capability/flow, and ... Professional development in DFT methodologies and foundry services * Direct impact on national ...
Hillsboro, OR · On-site
Drive quality improvements in ASIC DFT/DFM and ATPG validation methodology, capability/flow, and ... Professional development in DFT methodologies and foundry services * Direct impact on national ...
Beaverton, OR · On-site
As an ASIC STA Engineer, you will have responsibilities spanning all aspects of SoC design in terms of timing. Key responsibilities include timing sign-off, STA and sign-off flow development ...
Beaverton, OR · On-site
As an ASIC STA Engineer, you will have responsibilities spanning all aspects of SoC design in terms of timing. Key responsibilities include timing sign-off, STA and sign-off flow development ...
You are a seasoned ASIC Design Engineer with a robust background in design automation and a keen understanding of the intricate challenges in advanced semiconductor development. Your commitment to ...
You are a seasoned ASIC Design Engineer with a robust background in design automation and a keen understanding of the intricate challenges in advanced semiconductor development. Your commitment to ...
... As an ASIC STA Engineer, you will have responsibilities spanning all aspects of SoC design in terms of timing. Key responsibilities include timing sign-off, STA and sign-off flow development ...
... As an ASIC STA Engineer, you will have responsibilities spanning all aspects of SoC design in terms of timing. Key responsibilities include timing sign-off, STA and sign-off flow development ...
Hillsboro, OR · On-site
$127K/yr
You are a seasoned ASIC Design Engineer with a robust background in design automation and a keen understanding of the intricate challenges in advanced semiconductor development. Your commitment to ...
Hillsboro, OR · On-site
$127K/yr
You are a seasoned ASIC Design Engineer with a robust background in design automation and a keen understanding of the intricate challenges in advanced semiconductor development. Your commitment to ...
As a Firmware Development Engineer, you will play a pivotal role in shaping Intel's innovative ... Product Enablement (IP, tools, and methodologies), Custom ASIC (leveraging existing IP for custom ...
As a Firmware Development Engineer, you will play a pivotal role in shaping Intel's innovative ... Product Enablement (IP, tools, and methodologies), Custom ASIC (leveraging existing IP for custom ...
Beaverton, OR · On-site
$121.68K - $174.44K/yr
Participate in the entire product development lifecycle from definition to product release. Apply ... mixed signal ASIC and FPGA designs. Document design work, present results, and participate in ...
Beaverton, OR · On-site
$121.68K - $174.44K/yr
Participate in the entire product development lifecycle from definition to product release. Apply ... mixed signal ASIC and FPGA designs. Document design work, present results, and participate in ...
| Aspect | Asic Development Engineer | FPGA Design Engineer |
|---|---|---|
| Required Credentials | Bachelor's or Master's in Electrical Engineering, VLSI, or related fields; knowledge of ASIC design tools | Bachelor's or Master's in Electrical Engineering, Digital Design; familiarity with FPGA development tools |
| Work Environment | Designing and verifying custom silicon chips in semiconductor labs or R&D centers | Developing and testing FPGA-based solutions in hardware labs or embedded systems environments |
| Industry Usage | Used in semiconductor companies, integrated circuit design firms, and tech giants | Common in telecommunications, aerospace, and embedded systems industries |
While both roles involve digital hardware design, Asic Development Engineers focus on creating custom chips for high-performance applications, whereas FPGA Design Engineers work on programmable hardware solutions. Both require strong digital design skills and familiarity with hardware description languages, but their end products and development environments differ.
NVIDIA has been transforming computer graphics, PC gaming, and accelerated computing for more than 25 years. It's a unique legacy of innovation that's fueled by great technology-and amazing people.
Today, we're tapping into the unlimited potential of AI to define the next era of computing. An era in which our GPU acts as the brains of computers, robots, and self-driving cars that can understand the world. Doing what's never been done before takes vision, innovation, and the world's best talent. As an NVIDIAN, you'll be immersed in a diverse, supportive environment where everyone is inspired to do their best work. Come join the team and see how you can make a lasting impact on the world. At NVIDIA, we are leading the charge in developing groundbreaking technologies that redefine the future of computing. As an Senior ASIC Power Engineer in our Santa Clara, CA office, you will play a meaningful role in crafting the power architecture of our world-class products. This is an outstanding opportunity to join a team of highly dedicated individuals who thrive on innovation and collaboration.
What you'll be doing:
Join the NVIDIA Power Architecture Group handling the full range of power-related activities including ASIC energy evaluation, power architecture, low power development, power-aware verification, advanced power methodologies, UPF methodologies, power feature bring-up on silicon, and post-Si power correlation for NVIDIA's product lineup.
Support power analysis efforts by aiding in the architecture, creation, verification, and correlation of power estimation models/tools for NVIDIA's products.
Be part of the team that architects and builds system-level power features for optimizing the dynamic and leakage power dissipation for different use cases.
Work on power verification which includes structural, functional, and power-aware verification of power features of NVIDIA products by developing test plans, writing test cases, building test bench components like monitors, assertions, and coverage points, and owning verification convergence across RTL, Gates, and Silicon.
Validate the efficiency of the power features on silicon, conduct studies, and contribute to Performance/Watt improvement ideas.
Help develop power management solutions and foster innovation in energy efficiency throughout NVIDIA's product portfolio.
What we need to see:
B.Tech./M.Tech (or equivalent experience) with over 5 years of experience in power analysis, power development, power-aware verification, UPF methodologies, and power correlation.
Solid understanding of all power aspects, including full-chip power modeling, transistor-level leakage and dynamic characteristics in VLSI circuits.
Strong fundamentals in digital build flow and Verilog (especially low power RTL development).
Familiarity with low power build techniques such as multi-VT, clock gating, power gating, voltage islands, and Dynamic Voltage-Frequency Scaling (DVFS).
Solid experience in power estimation methods, processes, and algorithms.
Working experience with scripting languages like Python is a must.
Prior experience writing SW-driven power virus tests and silicon debug is necessary.
Experience in power supply and supply noise analysis and reduction is advantageous.
Must be an excellent collaborator and prepared to work with international groups from varied cultural origins in a dynamic environment.
Ways to stand out from the crowd:
Good debugging and problem-solving skills.
Strong communication abilities and the capability to work well with others.
Solid programming skills, ideally in C++ & Python.
Knowledge of lab equipment for power measurements, including oscilloscopes or DAQs, along with the capability to troubleshoot board-level power issues is a plus.
Widely considered to be one of the technology world's most desirable employers, NVIDIA offers highly competitive salaries and a comprehensive benefits package. As you plan your future, see what we can offer to you and your family www.nvidiabenefits.com/
#LI-Hybrid
Your base salary will be determined based on your location, experience, and the pay of employees in similar positions. The base salary range is 136,000 USD - 218,500 USD for Level 3, and 168,000 USD - 264,500 USD for Level 4.You will also be eligible for equity and benefits.
This posting is for an existing vacancy.
NVIDIA uses AI tools in its recruiting processes.
NVIDIA is committed to fostering a diverse work environment and proud to be an equal opportunity employer. As we highly value diversity in our current and future employees, we do not discriminate (including in our hiring and promotion practices) on the basis of race, religion, color, national origin, gender, gender expression, sexual orientation, age, marital status, veteran status, disability status or any other characteristic protected by law.Sourced by ZipRecruiter
NVIDIA has been transforming computer graphics, PC gaming, and accelerated computing for more than 25 years. It's a unique legacy of innovation that's fueled by great technology--and amazing people. Today, we're tapping into the unlimited potential of AI to define the next era of computing. An era in which our GPU acts as the brains of computers, robots, and self-driving cars that can understand the world. Doing what's never been done before takes vision, innovation, and the world's best talent.
Computer and electronic product manufacturing
10,000+ Employees
Santa Clara, CA, US
1993