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Altera Director Jobs (NOW HIRING)

Altera Corporation

Lead Product Planner

San Jose, CA · On-site

$159K - $230K/yr

About Altera At Altera™, our independence as the world's largest pure-play FPGA solutions provider gives us the focus, speed, and agility to innovate without compromise. With more than four decades ...

Harriscomputer

Director Product Management

Carolina, RI · Remote

$140K - $160K/yr

Altera Digital Health Director, Product Management US - EST time zone - Remote Overview Altera, a member of the N. Harris Computer Corporation family, delivers health IT solutions that support ...

Harris

Director Product Management

Carolina, RI · Remote

$140K - $160K/yr

Altera Digital Health Director, Product Management US - EST time zone - Remote Overview Altera, a member of the N. Harris Computer Corporation family, delivers health IT solutions that support ...

Altera

Physical Design Technical Lead

San Jose, CA

$209K - $299K/yr

Job Details: About Altera At Altera, our independence as the world's largest pure-play FPGA ... This is a high-visibility, high-impact position with a direct path to senior technical leadership.

Altera Corporation

Clocking Architect

San Jose, CA · On-site

What Altera Offers * The opportunity to shape clocking architecture for the world's most advanced programmable logic devices. * A collaborative, engineering-first culture with direct visibility into ...

Altera

Analog Circuit Design Engineer

San Jose, CA

$149K - $215K/yr

Job Details: About Altera At Altera, our independence as the world's largest pureplay FPGA ... Direct design experience with analog and mixed signal circuits like amplifiers, comparators ...

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Altera Director information

What is the difference between Altera Director vs FPGA Design Manager?

AspectAltera DirectorFPGA Design Manager
Required CredentialsBachelor's or Master's in Electrical Engineering, Computer Engineering, or related field; often requires leadership experienceBachelor's or Master's in Electrical Engineering, Computer Engineering, or related field; experience in FPGA design
Work EnvironmentLeadership role overseeing multiple teams or projects within FPGA/ASIC developmentHands-on FPGA design and team management within engineering teams
Employer & Industry UsageUsed in semiconductor companies, tech firms, and FPGA solution providersCommon in FPGA design firms, semiconductor companies, and R&D departments

The Altera Director typically holds a leadership position overseeing FPGA or semiconductor projects, focusing on strategic management and team coordination. In contrast, an FPGA Design Manager is more involved in the technical aspects of FPGA development while managing a team of engineers. Both roles require technical expertise, but the Director emphasizes strategic oversight, whereas the Manager focuses on design execution.

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Senior Design Verification Engineer

Senior Design Verification Engineer

Altera Corporation

San Jose, CA • On-site

$142K - $206K/yr

Full-time

Re-posted 3 days ago

Job description

Job Details:
Job Description:
Altera is responsible for High-Speed Protocol IP development, which includes participating in high-level product specifications, logic/RTL design and implementation, RTL verification, IP FPGA validation and debugging.
As Lead DV Engineer focusing on IP Verification & Validation, you will be responsible for carrying out design validation for Altera next generation IP's across the Altera FPGA IP product portfolios. The charter of IP verification & validation team is to verify and validate the IP for robust functionality from functional simulation. The verification and validation areas encompass IP's for high-speed transceiver protocols (Preferred - Ethernet/PCIe/CXL).
  • Create comprehensive verification and validation plan based on IP/FPGA architecture specifications and carry out all the IP validation tasks. The plan encompasses functional, system level and hardware verification and validation perspectives.
  • Developing IP/subsystem/system level testbench, create tests, and necessary coverage goals based on specification to verify the implementation. Writing directed and random test cases, debugging failures, filing and closing bugs.
  • Review verification and validation results against the coverage goals. Writing, analyzing and achieving coverage metrics.
  • Work with cross-functional teams and prepare/support IP functional validation tests for IP bring-up on actual FPGA development kits.
  • Creating and establishing IP subsystem/solution validation coverage strategy and standardized framework, drive system test design implementation and overall IP system validation on HW, maximizing FPGA hardware capability to bring substantial improvement to IP quality & usability for Altera FPGA IP product portfolios.
  • Developing verification and validation tools and flows, as needed.
  • Apply advanced techniques to achieve verification and validation with the highest quality, productivity, and time-to-market.

Salary Range
The pay range below is for Bay Area California only. Actual salary may vary based on a number of factors including job location, job-related knowledge, skills, experiences, trainings, etc. We also offer incentive opportunities that reward employees based on individual and company performance.
$142.6k - $206.5k USD
We use artificial intelligence to screen, assess, or select applicants for the position. Applicants must be eligible for any required U.S. export authorizations.
Qualifications:
Minimum Qualifications:
  • BS/MS in Electrical Engineering, Computer Engineering or a closely related field of study and 9+ years of industry experience.
  • 9+ years of experience developing verification collateral in Verilog, System Verilog and UVM.
  • 7+ years with Ethernet/PCIe/CXL protocol verification is required.
  • 7+ years in UVM Fluency is a must.
  • 7+ years of complex coverage driven random constraint UVM environments.
  • 7+ years of experience with High level Specification into test plan and developing tests cases.
  • 7+ years of experience of debugging skills to narrow down and isolate issue between RTL design and testbench or test case is required.
  • Good communication skills.

Job Type:
Regular
Shift:
Shift 1 (United States of America)
Primary Location:
San Jose, California, United States
Additional Locations:
Posting Statement:
All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

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