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Work From Home Asic Physical Design Engineer Jobs

K2 Space

Senior ASIC Physical Design Engineer

$170K - $250K/yr

Backed by $450M from leading investors including Altimeter Capital, Redpoint Ventures, T. Rowe ... Work with external physical design service providers and internal leads to review deliverables ...

K2 Space

Principal ASIC Physical Design Engineer

$190K - $280K/yr

Backed by $450M from leading investors including Altimeter Capital, Redpoint Ventures, T. Rowe ... Work with EDA vendors to debug and optimize tool flows, and evaluate new methodologies. * Support ...

MatX

ASIC/SOC CAD Engineer

Mountain View, CA · On-site +1

$175K - $362K/yr

... EMIR, physical verification) * This is a hybrid role that will require you to work from our ... Remote Perks We work remotely Monday & Friday, supported by home-tech setup, and remote wifi ...

Synopsys

ASIC Digital Design, Principal Engineer

Austin, TX · On-site +1

$166K - $249K/yr

Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning ... Collaborating closely with cross-functional teams, including analog design, physical design, and ...

Futran Tech Solutions Pvt. Ltd.

Physical Design Engineer

$139K - $143K/yr

Overall, 7 to 12 yrs of exp as a Physical Design Engineer. (Remote Opening) Must Have : Advance ... Must have hands-on experience on PnR Suite from Synopsys/Cadence(Innovus, ICC2). * Strong ...

K2 Space

Senior ASIC Design Verification Engineer

$170K - $250K/yr

Backed by $450M from leading investors including Altimeter Capital, Redpoint Ventures, T. Rowe ... Work closely with architecture, RTL design, DFT, firmware, physical design, and silicon validation ...

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Work From Home Asic Physical Design Engineer information

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$95K

$141.5K

How much do work from home asic physical design engineer jobs pay per year?

As of Jun 14, 2026, the average yearly pay for work from home asic physical design engineer in the United States is $139,408.00, according to ZipRecruiter salary data. Most workers in this role earn between $136,000.00 and $140,000.00 per year, depending on experience, location, and employer.

What does a typical day look like for a Work From Home ASIC Physical Design Engineer?

A typical day for a Work From Home ASIC Physical Design Engineer involves collaborating virtually with cross-functional teams to review design specifications, run synthesis and place-and-route tools, and resolve timing or power issues in the ASIC flow. You’ll spend much of your time working with EDA software, analyzing and optimizing chip layouts, and documenting your progress for project stakeholders. Regular video meetings and written updates are common to stay aligned with team goals and project timelines. This role requires strong communication skills and proactive engagement to maintain project momentum from a remote setting.

What is a Work From Home ASIC Physical Design Engineer job?

A Work From Home ASIC Physical Design Engineer designs and optimizes the physical layout of integrated circuits (ICs) while working remotely. They handle tasks such as floorplanning, placement, routing, and timing analysis to ensure the chip meets performance and power requirements. Using EDA tools, they collaborate with design and verification teams to resolve issues and optimize designs. Remote ASIC engineers must have strong technical skills, effective communication, and the ability to work independently.

What are the key skills and qualifications needed to thrive in the Work From Home Asic Physical Design Engineer position, and why are they important?

To thrive as a Work From Home ASIC Physical Design Engineer, you need strong expertise in digital design, ASIC implementation flows, and a degree in electrical or computer engineering. Proficiency with industry-standard EDA tools like Synopsys, Cadence, or Mentor Graphics and knowledge of scripting languages such as TCL or Perl is highly valued. Excellent communication, time management, and self-motivation are important for remote collaboration and effective project delivery. These skills ensure high-quality chip designs, efficient remote teamwork, and timely completion of complex engineering tasks.

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Work From Home Asic Physical Design Engineer jobs near you
Infographic showing various Work From Home Asic Physical Design Engineer job openings in the United States as of June 2026, with employment types broken down into 1% Locum Tenens, 36% Full Time, 61% Part Time, 1% Temporary, and 1% Contract. Highlights an 87% Physical, 5% Hybrid, and 8% Remote job distribution, with an average salary of $139,408 per year, or $67 per hour.

Senior ASIC Physical Design Engineer

K2 Space

Remote

$170K - $250K/yr

Full-time

Medical, Dental, Vision, Life, PTO

Posted 17 days ago

Job description

K2 is building the largest and highest-power satellites ever flown, unlocking performance levels previously out of reach across every orbit. Backed by $450M from leading investors including Altimeter Capital, Redpoint Ventures, T. Rowe Price, Lightspeed Venture Partners, Alpine Space Ventures, and others - with an additional $500M in signed contracts across commercial and US government customers - we're mass-producing the highest-power satellite platforms ever built for missions from LEO to deep space.
The rise of heavy-lift launch vehicles is shifting the industry from an era of mass constraint to one of mass abundance, and we believe this new era demands a fundamentally different class of spacecraft. Engineered to survive the harshest radiation environments and to fully capitalize on today's and tomorrow's massive rockets, K2 satellites deliver unmatched capability at constellation scale and across multiple orbits.
With multiple launches planned through 2026 and 2027, we're Building Bigger to develop the solar system and become a Kardashev Type II (K2) civilization. If you are a motivated individual who thrives in a fast-paced environment and you're excited about contributing to the success of a groundbreaking Series C space startup, we'd love for you to apply.
The Role
We are seeking a Senior ASIC Physical Design Engineer to help implement advanced SoCs that power next-generation satellite and space systems. In this role, you will contribute to the full physical design flow-from synthesis to GDSII-working closely with architecture, RTL, verification, and packaging teams. You'll be a key contributor in achieving timing closure, optimizing PPA, and supporting design integration with external partners. You will be part of a collaborative design team developing state-of-the-art mixed-signal SoCs to be hosted on some of the largest, most powerful, rapidly designed and rapidly manufactured satellites ever deployed in space. In your first 6 months, you will develop and implement new SoC sub-systems for satellite communications and beyond. In your first two years, you will have contributed to developing cutting-edge SoCs that will fly in space.
Responsibilities
  • Execute the complete physical design flow for complex SoC blocks and top-level integration, including synthesis, floorplanning, place & route, CTS, STA, and physical verification.
  • Perform timing closure and optimization across multiple corners and modes using industry-standard tools.
  • Collaborate with front-end, verification, and DFT teams to ensure clean handoff and predictable convergence.
  • Work with external physical design service providers and internal leads to review deliverables, resolve issues, and ensure schedule alignment.
  • Develop and maintain scripts and automation to improve flow efficiency and consistency.
  • Support physical sign-off activities including DRC/LVS, IR drop, EM, and power analysis.
  • Assist in chip-level integration, ECOs, and tapeout preparation.
  • Contribute to methodology development, tool evaluation, and flow documentation.
  • Support your product through production and spaceflight.

Required Qualifications
  • Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or related field.
  • 5-10 years of experience in ASIC physical design for complex SoCs.
  • Hands-on experience with industry-standard tools (Synopsys ICC2/Fusion Compiler, Cadence Innovus, or equivalent).
  • Strong understanding of timing analysis, power optimization, and physical verification flows.
  • Experience with hierarchical or flat SoC design methodologies.
  • Familiarity with FinFET technologies.
  • Working knowledge of DFT, UPF/CPF power intent, and ECO implementation.
  • Strong problem-solving skills and ability to work cross-functionally in fast-paced environments.

Preferred Qualifications
  • Exposure to radiation-hardened or space-qualified ASICs.
  • Experience with chip-package co-design or advanced packaging (2.5D/3D).
  • Familiarity with physical design service vendor management or offshore collaboration.
  • Experience with sign-off through TSMC.
  • Experience with Gate-All-Around technologies.
  • Experience working in cross-functional, geographically distributed teams.

Compensation and Benefits:
  • Base salary range for this role is $170,000 - $250,000 + equity in the company
  • Salary will be based on several factors including, but not limited to: knowledge and skills, education, and experience level
  • Comprehensive benefits package including paid time off, medical/dental/vision/ coverage, life insurance, paid parental leave, and many other perks

If you don't meet 100% of the preferred skills and experience, we encourage you to still apply! Building a spacecraft unlike any other requires a team unlike any other and non-traditional career twists and turns are encouraged!
If you need a reasonable accommodation as part of your application for employment or interviews with us, please let us know.
Export Compliance
As defined in the ITAR, "U.S. Persons" include U.S. citizens, lawful permanent residents (i.e., Green Card holders), and certain protected individuals (e.g., refugees/asylees, American Samoans). Please consult with a knowledgeable advisor if you are unsure whether you are a "U.S. Person."
The person hired for this role will have access to information and items controlled by U.S. export control regulations, including the export control regulations outlined in the International Traffic in Arms Regulation (ITAR). The person hired for this role must therefore either be a "U.S. person" as defined by 22 C.F.R. § 120.15 or otherwise eligible for a federally issued export control license.
Equal Opportunity
K2 Space is an Equal Opportunity Employer; employment with K2 Space is governed on the basis of merit, competence and qualifications and will not be influenced in any manner by race, color, religion, gender, national origin/ethnicity, veteran status, disability status, age, sexual orientation, gender identity, marital status, mental or physical disability or any other legally protected status.

About K2 Space

Sourced by ZipRecruiter

Industry

Guided missile and space vehicle manufacturing

Company size

11 - 50 Employees

Headquarters location

Los Angeles, CA, US

Year founded

2022

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