OR · On-site +1
$170K - $250K/yr
In this role, you will contribute to the full physical design flow-from synthesis to GDSII-working ... Work with external physical design service providers and internal leads to review deliverables ...
OR · On-site +1
$170K - $250K/yr
In this role, you will contribute to the full physical design flow-from synthesis to GDSII-working ... Work with external physical design service providers and internal leads to review deliverables ...
OR · On-site +1
$190K - $280K/yr
You will own the full physical design flow-from RTL handoff to GDSII-and collaborate closely with ... Work with EDA vendors to debug and optimize tool flows, and evaluate new methodologies. * Support ...
OR · On-site +1
$190K - $280K/yr
You will own the full physical design flow-from RTL handoff to GDSII-and collaborate closely with ... Work with EDA vendors to debug and optimize tool flows, and evaluate new methodologies. * Support ...
$170K - $250K/yr
Backed by over $1 billion in total funding from leading investors including Altimeter Capital ... Work with external physical design service providers and internal leads to review deliverables ...
$170K - $250K/yr
Backed by over $1 billion in total funding from leading investors including Altimeter Capital ... Work with external physical design service providers and internal leads to review deliverables ...
$190K - $280K/yr
Backed by over $1 billion in total funding from leading investors including Altimeter Capital ... Work with EDA vendors to debug and optimize tool flows, and evaluate new methodologies. * Support ...
$190K - $280K/yr
Backed by over $1 billion in total funding from leading investors including Altimeter Capital ... Work with EDA vendors to debug and optimize tool flows, and evaluate new methodologies. * Support ...
Irvine, CA · On-site +1
$200K - $300K/yr
Key Qualifications • Experience: 7+ to 15+ years of relevant ASIC physical design experience ... Advanced proficiency with industry-standard EDA tools from vendors like Cadence (e.g., Innovus ...
Irvine, CA · On-site +1
$200K - $300K/yr
Key Qualifications • Experience: 7+ to 15+ years of relevant ASIC physical design experience ... Advanced proficiency with industry-standard EDA tools from vendors like Cadence (e.g., Innovus ...
San Jose, CA · On-site +1
$200K - $300K/yr
Key Qualifications • Experience: 7+ to 15+ years of relevant ASIC physical design experience ... Advanced proficiency with industry-standard EDA tools from vendors like Cadence (e.g., Innovus ...
San Jose, CA · On-site +1
$200K - $300K/yr
Key Qualifications • Experience: 7+ to 15+ years of relevant ASIC physical design experience ... Advanced proficiency with industry-standard EDA tools from vendors like Cadence (e.g., Innovus ...
$150K - $300K/yr
... from the ground up. * Work at the cutting edge of advanced-node design, tackling some of the ... Remote-first culture with a company-provided computer and home office setup Compensation and future
$150K - $300K/yr
... from the ground up. * Work at the cutting edge of advanced-node design, tackling some of the ... Remote-first culture with a company-provided computer and home office setup Compensation and future
Santa Clara, CA · Remote
$100K - $500K/yr
A seasoned ASIC Physical Design Engineer with 5+ years at advanced nodes (7nm or below) and multiple successful tapeouts. * Strong in full-chip implementation, comfortable owning blocks from RTL to ...
Santa Clara, CA · Remote
$100K - $500K/yr
A seasoned ASIC Physical Design Engineer with 5+ years at advanced nodes (7nm or below) and multiple successful tapeouts. * Strong in full-chip implementation, comfortable owning blocks from RTL to ...
San Jose, CA · On-site +1
$159K - $164K/yr
Deliver physical design of an end-to-end IP or integration of ASIC/SoC design Minimum Qualifications: * Bachelor's degree in Electrical Engineering, with 5 years of relevant physical design ...
San Jose, CA · On-site +1
$159K - $164K/yr
Deliver physical design of an end-to-end IP or integration of ASIC/SoC design Minimum Qualifications: * Bachelor's degree in Electrical Engineering, with 5 years of relevant physical design ...
San Jose, CA · On-site +1
... from chip architecture to system performance at scale. Cornelis Networks delivers the world ... Physical Design teams. You must know "how the work gets done" to manage the people doing it.
San Jose, CA · On-site +1
... from chip architecture to system performance at scale. Cornelis Networks delivers the world ... Physical Design teams. You must know "how the work gets done" to manage the people doing it.
Austin, TX · On-site +1
... from chip architecture to system performance at scale. Cornelis Networks delivers the world ... Physical Design teams. You must know "how the work gets done" to manage the people doing it.
Austin, TX · On-site +1
... from chip architecture to system performance at scale. Cornelis Networks delivers the world ... Physical Design teams. You must know "how the work gets done" to manage the people doing it.
OR · On-site +1
... ASIC, Physical Design, CAD, Package Design, Software, DFT and other teams. What you'll be doing ... If so, we want to hear from you. Your base salary will be determined based on your location ...
OR · On-site +1
... ASIC, Physical Design, CAD, Package Design, Software, DFT and other teams. What you'll be doing ... If so, we want to hear from you. Your base salary will be determined based on your location ...
San Jose, CA · On-site +1
... from chip architecture to system performance at scale. Cornelis Networks delivers the world ... Define timing constraints for RTL blocks and work with Physical Design engineers to optimize timing ...
San Jose, CA · On-site +1
... from chip architecture to system performance at scale. Cornelis Networks delivers the world ... Define timing constraints for RTL blocks and work with Physical Design engineers to optimize timing ...
San Jose, CA · On-site +1
... from chip architecture to system performance at scale. Cornelis Networks delivers the world ... Define timing constraints for RTL blocks and work with Physical Design engineers to optimize timing ...
San Jose, CA · On-site +1
... from chip architecture to system performance at scale. Cornelis Networks delivers the world ... Define timing constraints for RTL blocks and work with Physical Design engineers to optimize timing ...
San Jose, CA · On-site +1
... from chip architecture to system performance at scale. Cornelis Networks delivers the world ... Collaborate with IP vendors, architecture, verification, physical design, and software teams to ...
San Jose, CA · On-site +1
... from chip architecture to system performance at scale. Cornelis Networks delivers the world ... Collaborate with IP vendors, architecture, verification, physical design, and software teams to ...
Austin, TX · On-site +1
... from chip architecture to system performance at scale. Cornelis Networks delivers the world ... Collaborate with IP vendors, architecture, verification, physical design, and software teams to ...
Austin, TX · On-site +1
... from chip architecture to system performance at scale. Cornelis Networks delivers the world ... Collaborate with IP vendors, architecture, verification, physical design, and software teams to ...
Sunnyvale, CA · On-site +1
$146K/yr
In this role, you will work at the intersection of EDA tooling, physical design, and power ... ASIC Engineer, Power Responsibilities: * Develop and maintain power analysis flows including ...
Sunnyvale, CA · On-site +1
$146K/yr
In this role, you will work at the intersection of EDA tooling, physical design, and power ... ASIC Engineer, Power Responsibilities: * Develop and maintain power analysis flows including ...
Austin, TX · On-site +1
$146K/yr
In this role, you will work at the intersection of EDA tooling, physical design, and power ... ASIC Engineer, Power Responsibilities: * Develop and maintain power analysis flows including ...
Austin, TX · On-site +1
$146K/yr
In this role, you will work at the intersection of EDA tooling, physical design, and power ... ASIC Engineer, Power Responsibilities: * Develop and maintain power analysis flows including ...
OR · On-site +1
This is our life's work, to amplify human creativity and intelligence. Make the choice to join us ... Ways to stand out from the crowd: Familiarity with ARM CPU and SoC system architecture ...
OR · On-site +1
This is our life's work, to amplify human creativity and intelligence. Make the choice to join us ... Ways to stand out from the crowd: Familiarity with ARM CPU and SoC system architecture ...
Richardson, TX · On-site +1
$122K/yr
Work closely with analog/mixed-signal, physical design, firmware, product, and customer-facing ... We specialize in advanced technology development, full-custom ASIC/SoC design, and electronics ...
Richardson, TX · On-site +1
$122K/yr
Work closely with analog/mixed-signal, physical design, firmware, product, and customer-facing ... We specialize in advanced technology development, full-custom ASIC/SoC design, and electronics ...
$95K - $99.2K
0% of jobs
$99.2K - $103.5K
0% of jobs
$103.5K - $107.7K
0% of jobs
$107.7K - $111.9K
0% of jobs
$111.9K - $116.1K
0% of jobs
$116.1K - $120.4K
0% of jobs
$120.4K - $124.6K
0% of jobs
$124.6K - $128.8K
0% of jobs
$128.8K - $133K
1% of jobs
$135.4K is the 25th percentile. Wages below this are outliers.
$133K - $137.3K
43% of jobs
The median wage is $137.7K / yr.
$137.3K - $141.5K
56% of jobs
$95K
$141.5K
A Work From Home ASIC Physical Design Engineer designs and optimizes the physical layout of integrated circuits (ICs) while working remotely. They handle tasks such as floorplanning, placement, routing, and timing analysis to ensure the chip meets performance and power requirements. Using EDA tools, they collaborate with design and verification teams to resolve issues and optimize designs. Remote ASIC engineers must have strong technical skills, effective communication, and the ability to work independently.
A typical day for a Work From Home ASIC Physical Design Engineer involves collaborating virtually with cross-functional teams to review design specifications, run synthesis and place-and-route tools, and resolve timing or power issues in the ASIC flow. You’ll spend much of your time working with EDA software, analyzing and optimizing chip layouts, and documenting your progress for project stakeholders. Regular video meetings and written updates are common to stay aligned with team goals and project timelines. This role requires strong communication skills and proactive engagement to maintain project momentum from a remote setting.
To thrive as a Work From Home ASIC Physical Design Engineer, you need strong expertise in digital design, ASIC implementation flows, and a degree in electrical or computer engineering. Proficiency with industry-standard EDA tools like Synopsys, Cadence, or Mentor Graphics and knowledge of scripting languages such as TCL or Perl is highly valued. Excellent communication, time management, and self-motivation are important for remote collaboration and effective project delivery. These skills ensure high-quality chip designs, efficient remote teamwork, and timely completion of complex engineering tasks.
Cities with the most Work From Home Asic Physical Design Engineer job openings:
States with the most job openings for Work From Home Asic Physical Design Engineer jobs include:
The top searched job categories for Work From Home Asic Physical Design Engineer jobs are:
$170K - $250K/yr
Full-time
Medical, Dental, Vision, Life, PTO
Re-posted 12 days ago
The Role
We are seeking a Senior ASIC Physical Design Engineer to help implement advanced SoCs that power next-generation satellite and space systems. In this role, you will contribute to the full physical design flow-from synthesis to GDSII-working closely with architecture, RTL, verification, and packaging teams. You'll be a key contributor in achieving timing closure, optimizing PPA, and supporting design integration with external partners. You will be part of a collaborative design team developing state-of-the-art mixed-signal SoCs to be hosted on some of the largest, most powerful, rapidly designed and rapidly manufactured satellites ever deployed in space. In your first 6 months, you will develop and implement new SoC sub-systems for satellite communications and beyond. In your first two years, you will have contributed to developing cutting-edge SoCs that will fly in space.
Responsibilities
Required Qualifications
Preferred Qualifications
Compensation and Benefits:
Sourced by ZipRecruiter
Guided missile and space vehicle manufacturing
11 - 50 Employees
Los Angeles, CA, US
2022
