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Work From Home Asic Physical Design Engineer Jobs

Purple Hires Inc

ASIC DFT Engineer

Plano, TX · Remote

Collaborate with RTL design, verification, physical design, STA, and silicon validation teams to ... Work on JTAG, boundary scan, iJTAG, SSN, and IP-level DFT integration. * Review RTL, synthesis, LEC ...

Purple Hires Inc

ASIC Engineer - Remote

Plano, TX · Remote

Collaborate with RTL design, verification, physical design, STA, and silicon validation teams to ... Work on JTAG, boundary scan, iJTAG, SSN, and IP-level DFT integration. * Review RTL, synthesis, LEC ...

New

Purple Hires Inc

Lead ASIC DFT Engineer

San Jose, CA · Remote

Collaborate with RTL design, verification, physical design, STA, and silicon validation teams to ... Work on JTAG, boundary scan, iJTAG, SSN, and IP-level DFT integration. * Review RTL, synthesis, LEC ...

K2 Space

Principal ASIC Design Verification Engineer

$190K - $285K/yr

Backed by $450M from leading investors including Altimeter Capital, Redpoint Ventures, T. Rowe ... Work closely with architecture, RTL design, DFT, firmware, physical design, and silicon validation ...

Purple Hires Inc

Lead ASIC DFT Engineer

Plano, TX · Remote

Collaborate with RTL design, verification, physical design, STA, and silicon validation teams to ... Work on JTAG, boundary scan, iJTAG, SSN, and IP-level DFT integration. * Review RTL, synthesis, LEC ...

Ethernovia, Inc.

Senior ASIC (Front-End) Design Engineer

OR · Remote

$200K - $300K/yr

... from micro-architecture specification, RTL, verification, synthesis, lint, CDC, LEC, and static ... Work with system architects, software, hardware, and verification engineers to plan, architect ...

Lockheed Martin

ASIC & FPGA Design Engineer

Orlando, FL · On-site +1

$114K - $158K/yr

What You Will Be Doing As the ASIC & FPGA Design Engineer you will own the entire layout flow-from ... parasitic aware physical designs.You will operate in a dual tool environment (Synopsys Custom ...

K2 Space

Senior ASIC Design Verification Engineer

$170K - $250K/yr

Backed by $450M from leading investors including Altimeter Capital, Redpoint Ventures, T. Rowe ... Work closely with architecture, RTL design, DFT, firmware, physical design, and silicon validation ...

Nvidia

Senior ASIC Design Engineer

Santa Clara, CA · On-site +1

... ranging from consumer graphics to self-driving cars and the growing field of artificial ... Exposure and firsthand work experience with design and verification tools (VCS or equivalent ...

Positron AI

Mid-End ASIC Engineer, Principal

$190K - $280K/yr

Partner closely with architecture, RTL, verification, physical design, DFT, IP providers, and ... from day one Visa Support This position is open to candidates currently authorized to work in the U.

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All JobsAsic Physical Design Engineer JobsWork From Home Asic Physical Design Engineer Jobs

Work From Home Asic Physical Design Engineer information

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$95K

$141.5K

How much do work from home asic physical design engineer jobs pay per year?

As of Aug 1, 2026, the average yearly pay for work from home asic physical design engineer in the United States is $139,408.00, according to ZipRecruiter salary data. Most workers in this role earn between $136,000.00 and $140,000.00 per year, depending on experience, location, and employer.

What does a typical day look like for a Work From Home ASIC Physical Design Engineer?

A typical day for a Work From Home ASIC Physical Design Engineer involves collaborating virtually with cross-functional teams to review design specifications, run synthesis and place-and-route tools, and resolve timing or power issues in the ASIC flow. You’ll spend much of your time working with EDA software, analyzing and optimizing chip layouts, and documenting your progress for project stakeholders. Regular video meetings and written updates are common to stay aligned with team goals and project timelines. This role requires strong communication skills and proactive engagement to maintain project momentum from a remote setting.

What is a Work From Home ASIC Physical Design Engineer job?

A Work From Home ASIC Physical Design Engineer designs and optimizes the physical layout of integrated circuits (ICs) while working remotely. They handle tasks such as floorplanning, placement, routing, and timing analysis to ensure the chip meets performance and power requirements. Using EDA tools, they collaborate with design and verification teams to resolve issues and optimize designs. Remote ASIC engineers must have strong technical skills, effective communication, and the ability to work independently.

What are the key skills and qualifications needed to thrive in the Work From Home Asic Physical Design Engineer position, and why are they important?

To thrive as a Work From Home ASIC Physical Design Engineer, you need strong expertise in digital design, ASIC implementation flows, and a degree in electrical or computer engineering. Proficiency with industry-standard EDA tools like Synopsys, Cadence, or Mentor Graphics and knowledge of scripting languages such as TCL or Perl is highly valued. Excellent communication, time management, and self-motivation are important for remote collaboration and effective project delivery. These skills ensure high-quality chip designs, efficient remote teamwork, and timely completion of complex engineering tasks.

More about Work From Home Asic Physical Design Engineer jobs
What cities are hiring for Work From Home Asic Physical Design Engineer jobs? Cities with the most Work From Home Asic Physical Design Engineer job openings:
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Work From Home Asic Physical Design Engineer jobs near you
Infographic showing various Work From Home Asic Physical Design Engineer job openings in the United States as of July 2026, with employment types broken down into 91% Full Time, and 9% Temporary. Highlights an 100% Remote job distribution, with an average salary of $139,408 per year, or $67 per hour.

ASIC DFT Engineer

Purple Hires Inc

Plano, TX • Remote

Contractor

Re-posted 5 days ago

Job description

Role: Lead ASIC DFT Engineer
Location: Remote, (Onsite)
Duration: Contract
Year of Exp: 8+ yrs to 15 yrs.
Job Description:
We are seeking a highly experienced Lead ASIC DFT Engineer to architect, implement, verify, and debug advanced DFT solutions for complex ASIC and SoC designs. This role requires deep technical ownership across DFT architecture, scan insertion, ATPG, MBIST/LBIST, JTAG, boundary scan, and post-silicon validation, along with the ability to lead cross-functional debug efforts and drive resolution of critical silicon issues. The ideal candidate will have strong hands-on expertise in DFT fundamentals, fault models, test coverage, diagnosis, and debug, as well as the ability to evaluate and adopt emerging DFT methodologies and architecture schemes to improve robustness, quality, and yield.
Key Responsibilities:
  • Lead DFT architecture, implementation, verification, and sign-off for complex ASIC and SoC designs.
  • Drive scan architecture, scan insertion, scan chain stitching, and scan compression workflows to achieve high coverage and robust testability.
  • Own MBIST/LBIST integration, implementation, verification, and debug across design and silicon bring-up phases.
  • Perform DFT debug, failure analysis, root-cause investigation, and fault coverage closure for complex silicon issues.
  • Develop and validate DFT constraints, including DFT SDC, timing checks, and DFT-specific timing analysis.
  • Collaborate with RTL design, verification, physical design, STA, and silicon validation teams to resolve integration and implementation issues.
  • Support ATPG pattern generation, ATPG simulations, DRC analysis, test coverage analysis, and diagnosis/debug.
  • Work on JTAG, boundary scan, iJTAG, SSN, and IP-level DFT integration.
  • Review RTL, synthesis, LEC, and physical design impacts on DFT implementation and test quality.
  • Act as a technical escalation point for advanced DFT and post-silicon debug issues.
  • Mentor junior and mid-level DFT engineers and promote best practices in DFT methodology and automation.
  • Develop scripts and automation using TCL, PERL, or Python to improve flow efficiency and debug productivity.
Required Skills & Qualifications:
  • Strong hands-on experience in ASIC DFT with end-to-end ownership.
  • Solid understanding of DFT fundamentals, fault models, test techniques, and test coverage concepts.
  • Deep expertise in scan architecture, ATPG, MBIST, LBIST, JTAG, boundary scan, and silicon debug.
  • Hands-on experience with Synopsys, Cadence, and Siemens/Mentor EDA tools.
  • Proven experience in scan insertion, ATPG setup, simulation, debug, and DRC analysis.
  • Experience with MBIST implementation and verification; SMS experience preferred.
  • Experience with scan architecture and scan chain stitching; Tessent/SSN experience preferred.
  • Strong understanding of PLLs, RTL design, synthesis flows, logical equivalence checking (LEC), and physical design implementation.
  • Proven post-silicon debug and silicon bring-up experience.
  • Exposure to large SoC designs, hierarchical DFT flows, and multi-domain integration challenges.
  • Strong communication skills and the ability to work independently with minimal ramp-up.
Preferred Experience:
  • MBIST post-silicon validation.
  • ATPG simulations and fault coverage debug.
  • DFT RTL, DFD, DFT verification, and IP-level DFT integration.
  • DFT SDC creation and DFT timing closure support.
  • Boundary scan, iJTAG, SSN, and design-for-debug methodologies.
  • TCL/PERL scripting for DFT automation, reporting, and debug.
  • Experience working across multiple ASIC technology nodes and complex product development cycles.
  • Familiarity with yield learning, diagnosis, and manufacturing test optimization.