ZipRecruiter

Log In

2

Work From Home Analog Layout Design Engineer Jobs

Tenstorrent

Analog Design Engineer

North, SC · On-site +1

$100K - $500K/yr

... may differ from the one in this posting. Who you are * A Analog/Mixed-Signal Design Engineer to ... who can work with architecture, analog, digital, verification, layout, and software teams to ...

Impinj

Senior Staff Design Engineer, IC Layout

Work closely with the analog and digital design teams on floor planning, pin placement, power ... Experience in custom analog, RF, and mixed-signal layout, with ability to lead complex ICs from ...

Sapsol Technologies Inc

Analog Design Engineer

$206K/yr

... Work closely with PCB layout and packaging teams • Prepare and review technical documentation (test procedures, specifications, ECOs, reports, etc.) • Collaborate with Engineering, Operations ...

IC Enable

RFIC Layout Design (TSMC 4nm)

Richardson, TX · On-site +1

You will work along our layout engineers and RF designers to build detailed transistor-level layout ... analog circuit blocks including bandgap/bias/LDO, ADC/DAC, baseband filters, modulators, power ...

EdgeTech

Be Seen First

Senior Electrical Design Engineer

West Wareham, MA · Remote

$140K - $150K/yr

... as lead for critical analog design elements to include low-noise analog front end, signal ... Work with board layout design engineers and mechanical engineers to create PCBs and integrated ...

Fresh Consulting

Sr. PCB Design Engineer

$70 - $80/hr

Work with the Hardware Engineering team to provide Schematic and PCB board designs ... Layouts range from simple to complex, multi-layer printed circuit boards containing analog, digital ...

next page

Showing results 1-20

All JobsAnalog Layout Design Engineer JobsWork From Home Analog Layout Design Engineer Jobs

Work From Home Analog Layout Design Engineer information

See salary details

$77K

$186.2K

$203K

How much do work from home analog layout design engineer jobs pay per year?

As of Jul 30, 2026, the average yearly pay for work from home analog layout design engineer in the United States is $186,238.00, according to ZipRecruiter salary data. Most workers in this role earn between $202,000.00 and $202,000.00 per year, depending on experience, location, and employer.

What is a Work From Home Analog Layout Design Engineer job?

A Work From Home Analog Layout Design Engineer is responsible for designing the physical layout of analog and mixed-signal integrated circuits (ICs) while working remotely. They translate circuit schematics into physical layouts, ensuring optimal performance, manufacturability, and reliability. This role requires expertise in layout design tools such as Cadence Virtuoso, DRC/LVS verification, and knowledge of semiconductor processes. Engineers collaborate virtually with circuit designers and verification teams to meet project specifications. Strong attention to detail and communication skills are essential for success in this remote role.

What are the key skills and qualifications needed to thrive in the Work From Home Analog Layout Design Engineer position, and why are they important?

To thrive as a Work From Home Analog Layout Design Engineer, you need expertise in analog circuit design, semiconductor physics, and IC layout methodologies, typically supported by a degree in electrical engineering or a related field. Proficiency with EDA tools such as Cadence Virtuoso, Mentor Graphics, or Synopsys Custom Compiler, and a solid understanding of DRC/LVS verification processes, is essential. Strong attention to detail, effective remote communication, and self-motivation are key soft skills for success in a home office setting. These abilities ensure accurate, high-quality designs, smooth team collaboration, and productivity in a remote work environment.

What are the typical day-to-day responsibilities of a Work From Home Analog Layout Design Engineer?

As a Work From Home Analog Layout Design Engineer, your daily tasks typically include creating and optimizing analog IC layout designs, running verification checks such as DRC and LVS, and collaborating with circuit designers and other team members through virtual meetings. You’ll often review and incorporate design feedback, document layout processes, and resolve technical challenges independently or with remote support. Regular communication via email, chat, and video calls is an integral part of the workflow to ensure alignment across distributed teams. This remote structure allows for flexibility, but it also requires strong self-management and proactive problem-solving to maintain effective progress and meet project deadlines.

More about Work From Home Analog Layout Design Engineer jobs
What cities are hiring for Work From Home Analog Layout Design Engineer jobs? Cities with the most Work From Home Analog Layout Design Engineer job openings:
What states have the most Work From Home Analog Layout Design Engineer jobs? States with the most job openings for Work From Home Analog Layout Design Engineer jobs include:
What job categories do people searching Work From Home Analog Layout Design Engineer jobs look for? The top searched job categories for Work From Home Analog Layout Design Engineer jobs are:
Work From Home Analog Layout Design Engineer jobs near you
Infographic showing various Work From Home Analog Layout Design Engineer job openings in the United States as of July 2026, with employment types broken down into 6% Internship, 69% Full Time, 6% Part Time, and 19% Contract. Highlights an 25% In-person, and 75% Remote job distribution, with an average salary of $186,238 per year, or $89.5 per hour.

High-Speed Analog Layout Design Engineer

Celero Communications, Inc.

San Jose, CA • On-site, Remote

$239K/yr

Full-time

Posted yesterday

New

Job description

Senior to Principal High-Speed Analog Layout Design Engineer roles
Locations: Irvine, CA or San Jose, CA or remote
About the Role
Celero Communication Inc. is an exciting and fast-growing start-up in the semiconductor industry, pushing boundaries with innovative technologies that power the world’s most advanced AI and data center infrastructure. As we scale rapidly, we are looking for a driven and resourceful High-Speed Analog Layout Engineer to be the backbone of our daily operations and a key partner in shaping our company culture.
We are seeking a Principal/Senior Analog Layout Engineer to drive the layout design of complex analog and mixed-signal IP blocks that are at the heart of our advanced optical communication systems. As a key member of the Analog & Mixed-Signal (AMS) design team, you will lead layout development of critical blocks such as ADCs, DACs, PLLs, and other high-performance analog/mixed-signal circuits. You will interface closely with circuit designers, CAD/PDK teams, and other layout engineers to ensure first-pass silicon success. This is a hands-on technical role ideal for someone who thrives in a fast-paced environment and enjoys mentoring others while contributing directly to cutting-edge chip development.
Key Responsibilities
• Lead and own the physical layout design of complex analog/mixed-signal macros (e.g., ADCs, DACs, PLLs), from floor planning through final verification
• Collaborate closely with schematic designers to create optimal layout solutions considering performance, matching, symmetry, and reliability
• Mentor and guide junior layout engineers/contractors across multiple time zones, enforcing best practices in layout design and verification
• Perform and debug full hierarchy LVS, DRC, PERC, ERC, and other signoff checks using industry-standard tools (Pegasus, Calibre, etc.)
• Contribute to chip-level planning including top-level floor planning, block integration, power grid implementation, and signal routing
• Participate in layout design reviews and provide technical leadership for layout quality, verification completeness, and schedule adherence
• Support automation initiatives through scripting and tool customization (SKILL, TCL, Python is a plus)
Required Qualifications
• Minimum 10+ years of hands-on analog/mixed-signal layout design experience in advanced CMOS/FinFET technologies
• Proven track record of top level integration IP layout macros and preparing IPs for handoff to Physical Design
• Proven leadership in owning major IP layout macros or full-chip-level layout at FinFET nodes (TSMC preferred)
• At least 1 year of experience with TSMC FinFET process nodes (N3, N5, N7, or N16)
• Deep understanding of device physics, layout-dependent effects (LOD, WPE, OSE, LDE, etc.), and their impact on circuit performance
• Strong expertise in layout best practices for device matching, noise isolation, ESD protection, symmetry, and parasitic minimization
• Proficiency in floor planning, hierarchical block integration, routing strategy, and power/ground grid design
• Expertise with Cadence Virtuoso, Calibre, Pegasus, and other layout and verification tools
• Familiarity with layout verification flows, including LVS, DRC, PERC, Density, DFM, ERC, and Antenna rules
• Experience working in collaborative environments with international and remote teams
• Strong documentation and communication skills with the ability to clearly present layout trade-offs and status to cross-functional teams
• Experience using revision control systems for layout design management
Preferred Qualifications
• Exposure to optical or high-speed analog interfaces is a strong plus
• Working knowledge of SKILL, TCL, or Python for layout automation or design flow optimization
• Proven ability to collaborate with international teams (U.S., Canada, Argentina)
• Strong organizational skills with high attention to detail and follow-through
• Ability to multi-task and prioritize in a fast-paced, dynamic environment
• Proactive, eager-to-learn mindset with excellent problem-solving skills
What We Offer
• The chance to play a foundational role at a high-growth semiconductor start-up
• Exposure to a wide variety of cross functional teams
• A collaborative, international team culture where ideas and initiative are valued
• The opportunity to grow alongside Celero as we scale and shape the future of our industry
• A foundational role at a fast-growing semiconductor start-up shaping the future of AI and data center connectivity
Note: Since we have several roles available, candidate job level will be evaluated during interview process.