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Analog Ic Layout Designer Jobs (NOW HIRING)

Neuralink

Analog IC Layout Engineer

Fremont, CA

You will have the opportunity to collaborate closely with chip designers, electrical engineers, algorithms engineers, and software engineers on a small, agile team. As an Analog IC Layout Engineer ...

Neuralink

Analog IC Layout Engineer

Fremont, CA · On-site

$83K - $139K/yr

You will have the opportunity to collaborate closely with chip designers, electrical engineers, algorithms engineers, and software engineers on a small, agile team. As an Analog IC Layout Engineer ...

Analog Devices

Lead Analog IC Layout Engineer

Wilmington, MA · On-site

$134K - $201K/yr

Lead Analog IC Layout Engineer About the ATE Group: The Automatic Test Equipment (ATE) organization ... As a Lead Designer, Layout, you hold a senior technical position working on our most complex layout ...

Analogdevices

$134K - $201K/yr

Lead Analog IC Layout Engineer About the ATE Group: The Automatic Test Equipment (ATE) organization ... As a Lead Designer, Layout, you hold a senior technical position working on our most complex layout ...

SRI International

Analog IC Design Engineer

Princeton, NJ · On-site

$104K - $137K/yr

Overview SRI's Integrated Systems & Solutions (InSyS) Division designs leading-edge R&D ... Experience in analog IC layout to address DRC, LVS, matching, shielding, electromigration, IR drops ...

SRI International

Analog IC Design Engineer

Princeton, NJ

$104K - $137K/yr

SRI's Integrated Systems & Solutions (InSyS) Division designs leading-edge R&D technologies that ... Experience in analog IC layout to address DRC, LVS, matching, shielding, electromigration, IR drops ...

Glow Networks

Analog Layout Engineer

Santa Clara, CA · On-site

$237K/yr

Senior layout designer, will be responsible for layout of high-performance analog cores such as ... Responsibilities include leading IC layout of cutting-edge high-performance, high-speed CMOS ...

Skyworks

Sr. Principal IC Layout Designer

Cedar Rapids, IA · On-site

$114K - $220K/yr

Job Title: Sr. Principal IC Layout Designer Posting Start Date: 5/27/26 Job Location(s): Cedar ... Skyworks is an innovator of high-performance analog semiconductors whose solutions are powering the ...

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Analog Ic Layout Designer information

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How much do analog ic layout designer jobs pay per hour?

As of Jun 22, 2026, the average hourly pay for analog ic layout designer in the United States is $41.30, according to ZipRecruiter salary data. Most workers in this role earn between $17.55 and $58.41 per hour, depending on experience, location, and employer.

What is the difference between Analog Ic Layout Designer vs Digital IC Layout Designer?

AspectAnalog IC Layout DesignerDigital IC Layout Designer
CredentialsDegree in Electrical Engineering or related field, certifications in IC designDegree in Electrical Engineering or related field, certifications in IC design
Work EnvironmentSemiconductor companies, design houses, R&D labsSemiconductor companies, design houses, R&D labs
Industry UsageAnalog, mixed-signal, RF circuitsDigital circuits, microprocessors, memory chips
Design FocusAnalog signal integrity, low noise, high precisionLogic functionality, high speed, power optimization

Both roles require similar educational backgrounds and work environments, but they focus on different circuit types. Analog IC Layout Designers specialize in analog and mixed-signal circuits, emphasizing signal quality and precision, while Digital IC Layout Designers focus on digital logic and high-speed data processing. Understanding these differences helps in choosing the right career path or job search focus.

What are the key skills and qualifications needed to thrive as an Analog IC Layout Designer, and why are they important?

To thrive as an Analog IC Layout Designer, you need a strong background in electrical engineering principles, semiconductor physics, and experience with analog circuit design, typically supported by a relevant degree. Familiarity with industry-standard EDA tools such as Cadence Virtuoso, Mentor Graphics, and knowledge of design verification and DRC/LVS checks are crucial. Attention to detail, problem-solving abilities, and effective teamwork are important soft skills in this role. These skills ensure that complex analog circuits are designed efficiently, meet performance specifications, and are manufacturable with high yield.

What are some common challenges faced by Analog IC Layout Designers during the design process?

Analog IC Layout Designers often encounter challenges such as managing parasitic effects, ensuring proper matching of critical components, and optimizing layout for both performance and area efficiency. They must pay close attention to design rules, spacing, and symmetry, especially for sensitive analog circuits like amplifiers or oscillators. Collaboration with circuit designers is key to resolving performance issues, and frequent design reviews help catch layout-related problems early in the process.

What are Analog IC Layout Designers?

Analog IC Layout Designers are specialized engineers who create the physical layouts for integrated circuits (ICs) that handle analog signals. They translate circuit schematics into detailed geometric patterns that can be fabricated on semiconductor chips, ensuring optimal performance, reliability, and manufacturability. Their work involves close collaboration with circuit designers to meet specifications for power, area, and noise while adhering to foundry design rules. Analog IC layout requires deep knowledge of semiconductor processes, electronic design automation (EDA) tools, and analog circuit behavior.
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Analog Ic Layout Designer jobs near you
Infographic showing various Analog Ic Layout Designer job openings in the United States as of June 2026, with employment types broken down into 81% Full Time, 16% Part Time, and 3% Contract. Highlights an 94% Physical, 2% Hybrid, and 4% Remote job distribution, with an average salary of $85,906 per year, or $41.3 per hour.
Analog IC Layout Engineer

Analog IC Layout Engineer

Neuralink

Fremont, CA

Other

Posted 23 days ago

Job description

Team Description:

The Brain Interfaces Soc Department delivers chip architecture and silicon implementation of neural recording and stimulation system-on-chip (SoC) for high-bandwidth brain-computer interfaces. We have crafted a team of exceptional engineers whose mission is to push the frontiers of what is possible today and define the future.

Job Description and Responsibilities:

We are looking for experienced and hands-on engineers with a creative and initiative mindset, who are interested in exploring the next-generation chip design with advanced architectures and hardware accelerators with a goal of enhancing the energy efficiency, information entropy, and scalability of our wireless brain-computer interfaces towards the physical limit of silicon technology. The ideal candidates are energetic people who get excited about building things, are highly analytical, and enjoy tackling new problems. You will have the opportunity to collaborate closely with chip designers, electrical engineers, algorithms engineers, and software engineers on a small, agile team. As an Analog IC Layout Engineer, your responsibilities will include:

  • Crafting state-of-the-art layouts for mixed-signal and analog circuits
    • Amplifiers
    • Filters
    • Switched capacitor circuits
    • Oscillators
    • Data converters
    • Power management circuits
  • Reviewing layout floorplans and analyzing high-fidelity circuits with circuit engineers
  • Physical verification of custom IC mask layouts (LVS, DRC, ERC)

Required Qualifications:

  • 2+ years of experience in analog and mixed-signal IC layout design
  • 1+ year experience with FinFET technologies
  • Ability to identify the best approach to solving problems

Preferred Qualifications:

  • Programming/scripting knowledge in SKILL, TCL, Shell, C/C++, and/or Python
  • Proven expertise in implementing analog and mixed-signal layout designs, achieving tight matching, low noise, and low power consumption
  • Understanding on failure-prone circuit and layout structures
  • Experience with analog DFM standards
  • Experience with layout P-cell design and implementation
  • Experience with layout automation 

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