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Vlsi Design Verification Engineer Jobs (NOW HIRING)

Sivaltech

Design Verification Engineer

San Diego, CA · On-site

$144K - $176K/yr

Design Verification Engineer Location: Bay Area, CA (Onsite/Hybrid) Experience: 8+ Years Job Summary We are seeking an experienced Design Verification Engineer with strong expertise in ASIC/SoC ...

Apple

PHY Design Verification Engineer

Bodega Bay, CA

$122K - $214K/yr

  • Medical

  • Dental

  • Retirement

... VLSI/RTL design and integration, Design Verification, Emulation, Test and Validation, and FW/SW engineering. Description In this highly visible role, you will be at the center of a silicon design ...

Apple

Wireless Design Verification Engineer

Bodega Bay, CA

$122K - $214K/yr

  • Medical

  • Dental

  • Retirement

... VLSI/RTL design and integration, Design Verification, Emulation, Test and Validation, and FW/SW engineering. Description In this highly visible role, you will be at the center of a silicon design ...

Apple

PHY Design Verification Engineer

Bodega Bay, CA

$122K - $214K/yr

  • Medical

  • Dental

  • Retirement

... VLSI/RTL design and integration, Design Verification, Emulation, Test and Validation, and FW/SW engineering. Description In this highly visible role, you will be at the center of a silicon design ...

HCP ONE LLC

Design Verification Engineer

San Jose, CA · On-site

$159K - $194K/yr

Design Verification Engineer Location: San Jose, CA Experience: 8+ Years Type: Contract Description: This requirement is for a Senior Design Verification (DV) Engineer focused on verifying complex ...

Arrow Electronics

Design Verification Engineer

Denver, CO · On-site

$167K - $184K/yr

  • Medical

  • Dental

  • Vision

  • Retirement

  • PTO

Design Verification Engineer Develop strategies for verification by understanding design architecture and design specifications. Capture all requirements/features of design to create functional ...

Apple Inc.

PHY Design Verification Engineer

Cupertino, CA · On-site

$129.30 - $225.30/hr

  • Medical

  • Dental

  • Retirement

... VLSI/RTL design and integration, Design Verification, Emulation, Test and Validation, and FW/SW engineering. Description In this highly visible role, you will be at the center of a silicon design ...

Apple Inc.

Wireless Design Verification Engineer

Waltham, MA · On-site

$184.70 - $324.80/hr

  • Medical

  • Dental

  • Retirement

... VLSI/RTL design and integration, Design Verification, Emulation, Test and Validation, and FW/SW engineering. Description In this highly visible role, you will be at the center of a silicon design ...

Apple Inc.

Wireless Design Verification Engineer

Cupertino, CA · On-site

$129.30 - $225.30/hr

  • Medical

  • Dental

  • Retirement

... VLSI/RTL design and integration, Design Verification, Emulation, Test and Validation, and FW/SW engineering. Description In this highly visible role, you will be at the center of a silicon design ...

Apple

GPU Formal Design Verification Engineer

Austin, TX · On-site

$134K - $164K/yr

Experience with CPU or GPU design architectures, VLSI circuits, and digital logic design. Experience with formal verification tools, such as JasperGold, IFV, etc. Experience in programming/scripting ...

Apple Inc.

Wireless Design Verification Engineer

San Diego, CA · On-site

$122.70 - $214.30/hr

  • Medical

  • Dental

  • Retirement

... VLSI/RTL design and integration, Design Verification, Emulation, Test and Validation, and FW/SW engineering. Description In this highly visible role, you will be at the center of a silicon design ...

Correct Designs

Design Verification Engineer

Austin, TX · On-site

$134K - $164K/yr

  • Medical

  • Retirement

Design Verification Engineer Looking for new challenges? Would you like the variety of a contract position along with long term stability and benefits? Correct Designs can give it all to you. Correct ...

Lorven Technologies

Design verification Engineer

San Jose, CA · On-site

$158K - $192K/yr

Design Verification Engineer Location: San Jose, CA We are seeking DV engineers to verify complex internal IP blocks such as compute engines, accelerators, and custom logic within SoC environments.

Apple

GPU Formal Design Verification Engineer

Austin, TX

$134K - $164K/yr

Experience with CPU or GPU design architectures, VLSI circuits, and digital logic design. Experience with formal verification tools, such as JasperGold, IFV, etc. Experience in programming/scripting ...

Apple

C - Focused Design Verification Engineer

San Diego, CA

$175K - $308K/yr

  • Medical

  • Dental

  • Retirement

... VLSI/RTL design and integration, Emulation, Design Verification, Test and Validation, and FW/SW engineering. Description As a C- Focused Design Verification Engineer, you will be at the center of a ...

Correct Designs

Design Verification Engineer

Austin, TX · On-site

$134K - $164K/yr

  • Medical

  • Retirement

Design Verification Engineer Looking for new challenges? Would you like the variety of a contract position along with long term stability and benefits? Correct Designs can give it all to you. Correct ...

Intel

Design Verification Engineer

Santa Clara, CA

$141K - $200K/yr

  • Medical

  • Retirement

  • PTO

Intel is seeking a Design Verification Engineer for the Silicon Chassis team. In this role, you will contribute to verification of next-generation interconnect and chassis IPs that scale across ...

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Showing results 41-60

All JobsVlsi Design Verification Engineer Jobs

Vlsi Design Verification Engineer information

See salary details

$105.5K

$149.2K

$167K

How much do vlsi design verification engineer jobs pay per year?

As of Aug 16, 2026, the average yearly pay for vlsi design verification engineer in the United States is $149,150.00, according to ZipRecruiter salary data. Most workers in this role earn between $136,000.00 and $166,000.00 per year, depending on experience, location, and employer.

What are some common challenges faced by VLSI design verification engineers during the verification process?

VLSI Design Verification Engineers often encounter challenges such as managing increasingly complex system-on-chip (SoC) designs, ensuring thorough test coverage, and debugging intricate functional issues. Coordinating with cross-functional teams—like design, software, and validation—is essential to align test plans and resolve ambiguities quickly. Additionally, keeping up with evolving verification methodologies and tools (such as UVM or SystemVerilog) requires a commitment to continuous learning, but offers strong career growth opportunities for those who master them.

What are the key skills and qualifications needed to thrive as a VLSI design verification engineer?

To thrive as a VLSI Design Verification Engineer, you need a solid background in digital logic design, computer architecture, and verification methodologies, typically supported by a degree in electrical engineering or a related field. Proficiency with hardware description languages like Verilog or VHDL, simulation tools such as ModelSim or Synopsys VCS, and familiarity with UVM or SystemVerilog are commonly required. Strong analytical thinking, attention to detail, and effective communication are crucial soft skills for identifying design flaws and collaborating with cross-functional teams. These skills and qualifications ensure accurate, reliable chip designs and efficient project execution in the competitive semiconductor industry.

What is the difference between Vlsi Design Verification Engineer vs Vlsi Design Engineer?

AspectVlsi Design Verification EngineerVlsi Design Engineer
Primary FocusVerifying the correctness of VLSI designs through testing and simulationCreating and implementing VLSI chip designs and architectures
Skills & CertificationsHardware description languages (HDL), verification tools, scripting, knowledge of verification methodologiesHDL, digital design, synthesis, timing analysis, and physical design skills
Work EnvironmentDesign teams, verification labs, simulation environmentsDesign teams, synthesis and implementation tools, physical design environments

While both roles require HDL knowledge and work within VLSI teams, the Vlsi Design Verification Engineer primarily focuses on testing and validating designs, whereas the Vlsi Design Engineer is responsible for creating and implementing the actual chip designs.

What is a VLSI design verification engineer?

A VLSI Design Verification Engineer is a specialist responsible for ensuring that integrated circuits (ICs) and systems-on-chip (SoCs) meet their design specifications before manufacturing. They use various verification methodologies, such as simulation, formal verification, and hardware emulation, to identify and fix functional errors in digital designs. Their role is critical in the semiconductor industry to ensure product quality, reduce costly re-spins, and speed up time-to-market. They often work closely with design engineers, using tools like SystemVerilog, UVM, and other verification frameworks.
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Vlsi Design Verification Engineer jobs near you
Infographic showing various Vlsi Design Verification Engineer job openings in the United States as of August 2026, with employment types broken down into 50% Full Time, and 50% Contract. Highlights an 75% In-person, and 25% Remote job distribution, with an average salary of $149,150 per year, or $71.7 per hour.

Design Verification Engineer

Sivaltech

San Diego, CA • On-site

$144K - $176K/yr

Other

Posted 12 days ago

Job description

Design Verification Engineer

Location: Bay Area, CA (Onsite/Hybrid)
Experience: 8+ Years

Job Summary

We are seeking an experienced Design Verification Engineer with strong expertise in ASIC/SoC verification to join our semiconductor team. The ideal candidate will have extensive experience in SystemVerilog, UVM, and protocol verification, with a proven track record of developing robust verification environments and achieving coverage closure.

Key Responsibilities

  • Develop and execute comprehensive verification plans for ASIC/SoC designs.

  • Build reusable UVM-based verification environments, testbenches, scoreboards, checkers, and assertions.

  • Create and execute directed and constrained-random test cases.

  • Perform functional, code, assertion, and toggle coverage analysis and drive coverage closure.

  • Debug RTL and simulation issues in collaboration with design teams.

  • Verify complex IPs and SoCs at block, subsystem, and chip level.

  • Work closely with RTL designers, architects, and physical design teams throughout the development lifecycle.

  • Participate in regression execution, bug tracking, and verification sign-off.

Required Skills

  • 8+ years of ASIC/SoC Design Verification experience.

  • Strong expertise in SystemVerilog and UVM.

  • Excellent knowledge of Verilog and digital design fundamentals.

  • Experience with industry-standard simulators such as Synopsys VCS, Cadence Xcelium, or Siemens QuestaSim.

  • Strong debugging and scripting skills using Python, Perl, Shell, or Tcl.

  • Experience with assertions (SVA), constrained-random verification, and functional coverage.

  • Familiarity with version control systems such as Git.

Preferred Experience

  • Chip-level and SoC verification.

  • Verification of high-speed bus protocols such as AXI, AHB, APB, PCIe, USB, Ethernet, DDR, MIPI, or UCIe.

  • Low-power verification using UPF/CPF.

  • Experience with emulation or FPGA prototyping is a plus.

Education

Bachelor''s or Master''s degree in Electronics Engineering, Computer Engineering, or a related field.

Employment Type: Full-Time

If you are passionate about ASIC verification and have hands-on experience with modern verification methodologies, we''d love to hear from you.

Apply