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Vlsi Design Verification Engineer Jobs in Washington, DC

Grammar LLC

FPGA/ASIC Verification Engineer

Columbia, MD · Hybrid

$110K - $200K/yr

FPGA/ASIC Verification Engineer Job Schedule: 9/80: Employees work 9 out of every 14 days ... Perform FPGA design verification and validation of embedded electronic communication. Assist in ...

L3HHCM20

FPGA/ASIC Verification Engineer 1

Columbia, MD · Hybrid

$106.50K - $197.50K/yr

Senior Specialist, Electrical Engineer - FPGA/ASIC Verification Engineer Job Code: 37168 Job ... Perfrom FPGA design verification and validation of embedded electronic communication. * Assist in ...

Apple

Hardware Technologies PhD Internships

Washington, DC · On-site

$139.80K - $184.50K/yr

... VLSI, design, logic design, or circuit design * Understanding of formal methods or verification * Camera/touch/display engineering: optics, flat panel/HW, touch mechanical design; design and ...

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Vlsi Design Verification Engineer information

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$119.4K

$168.9K

$189.1K

How much do vlsi design verification engineer jobs pay per year?

As of May 28, 2026, the average yearly pay for vlsi design verification engineer in Washington, DC is $168,864.00, according to ZipRecruiter salary data. Most workers in this role earn between $154,000.00 and $187,900.00 per year, depending on experience, location, and employer.

What are the key skills and qualifications needed to thrive as a VLSI Design Verification Engineer, and why are they important?

To thrive as a VLSI Design Verification Engineer, you need a solid background in digital logic design, computer architecture, and verification methodologies, typically supported by a degree in electrical engineering or a related field. Proficiency with hardware description languages like Verilog or VHDL, simulation tools such as ModelSim or Synopsys VCS, and familiarity with UVM or SystemVerilog are commonly required. Strong analytical thinking, attention to detail, and effective communication are crucial soft skills for identifying design flaws and collaborating with cross-functional teams. These skills and qualifications ensure accurate, reliable chip designs and efficient project execution in the competitive semiconductor industry.

What are some common challenges faced by VLSI Design Verification Engineers during the verification process?

VLSI Design Verification Engineers often encounter challenges such as managing increasingly complex system-on-chip (SoC) designs, ensuring thorough test coverage, and debugging intricate functional issues. Coordinating with cross-functional teams—like design, software, and validation—is essential to align test plans and resolve ambiguities quickly. Additionally, keeping up with evolving verification methodologies and tools (such as UVM or SystemVerilog) requires a commitment to continuous learning, but offers strong career growth opportunities for those who master them.

What is a VLSI Design Verification Engineer?

A VLSI Design Verification Engineer is a specialist responsible for ensuring that integrated circuits (ICs) and systems-on-chip (SoCs) meet their design specifications before manufacturing. They use various verification methodologies, such as simulation, formal verification, and hardware emulation, to identify and fix functional errors in digital designs. Their role is critical in the semiconductor industry to ensure product quality, reduce costly re-spins, and speed up time-to-market. They often work closely with design engineers, using tools like SystemVerilog, UVM, and other verification frameworks.

What is the difference between Vlsi Design Verification Engineer vs Vlsi Design Engineer?

AspectVlsi Design Verification EngineerVlsi Design Engineer
Primary FocusVerifying the correctness of VLSI designs through testing and simulationCreating and implementing VLSI chip designs and architectures
Skills & CertificationsHardware description languages (HDL), verification tools, scripting, knowledge of verification methodologiesHDL, digital design, synthesis, timing analysis, and physical design skills
Work EnvironmentDesign teams, verification labs, simulation environmentsDesign teams, synthesis and implementation tools, physical design environments

While both roles require HDL knowledge and work within VLSI teams, the Vlsi Design Verification Engineer primarily focuses on testing and validating designs, whereas the Vlsi Design Engineer is responsible for creating and implementing the actual chip designs.

What are popular job titles related to Vlsi Design Verification Engineer jobs in Washington, DC? For Vlsi Design Verification Engineer jobs in Washington, DC, the most frequently searched job titles are:
What job categories do people searching Vlsi Design Verification Engineer jobs in Washington, DC look for? The top searched job categories for Vlsi Design Verification Engineer jobs in Washington, DC are:
Vlsi Design Verification Engineer jobs near you
Infographic showing various Vlsi Design Verification Engineer job openings in Washington, DC as of May 2026, with employment types broken down into 2% Internship, 91% Full Time, 2% Part Time, and 5% Contract. Highlights an 84% In-person, 7% Hybrid, and 9% Remote job distribution, with an average salary of $168,864 per year, or $81.2 per hour.
FPGA/ASIC Verification Engineer

FPGA/ASIC Verification Engineer

Grammar LLC

Columbia, MD • Hybrid

$110K - $200K/yr

Full-time

Medical, Retirement, PTO

This job post has expired today. Applications are no longer accepted.

Job description

Role: FPGA/ASIC Verification Engineer 
Job Schedule: 9/80: Employees work 9 out of every 14 days – totaling 80 hours worked – and have every other Friday off OR 5/8: Employees work 8 hours per day, 5 days a week

Job Description:

Join our team at the company and play a critical role in developing secure, cutting-edge tactical communication systems that protect those who protect us. As an FPGA Verification Engineer, you’ll collaborate with a talented, mission-driven team, verifying next-generation FPGA solutions for our radios used by military and first responders worldwide. This is a hands-on opportunity to grow your expertise in UVM, advanced verification methodologies, and complex communication systems—while enjoying work-life balance with flexible schedules and every other Friday off.

You will function primarily in an FPGA verification role, working in a cooperative team environment to verify and test embedded FPGA firmware for radio communication systems. We're seeking familiarity with a coverage-driven verification methodology from planning through closure as well as knowledge of industry standard interfaces. You will be required to analyze requirements, create test specifications/plans, write tests in System Verilog within a UVM test bench framework, and verify designs meet requirements. You will work with cross functional teams to verify FPGA designs for radio product development projects.

Essential Functions:

Perform FPGA design verification and validation of embedded electronic communication.

Assist in development of high-level and detailed verification test plans consistent with system requirements and specifications.

Develop self-checking test benches for FPGA design verification and validation using System Verilog.

Develop Agents, Test sequences, Cover groups, Predictors, Scoreboards.

Develop randomized and directed tests to achieve closure on functional coverage and provide feedback to team to reach functional coverage goals.

Develop high-level and detailed verification test plans and test benches consistent with system requirements and specifications.

Work with cross functional teams as needed to define and verify product and design requirements.

Prepare design and implementation reviews. Present technical briefings and status to internal and external customers.

Ability to obtain and maintain US Security Clearance.

Qualifications:

Bachelor’s Degree and minimum 6 years of prior relevant experience. Graduate Degree and a minimum of 4 years of prior related experience. In lieu of a degree, minimum of 10 years of prior related experience.

Experience developing and verifying FPGA/ASIC based embedded system solutions.

Preferred Additional Skills:

Demonstrated ability to analyze and debug FPGA firmware and related hardware issues.

Working knowledge of Ethernet Standard and design experience related to Ethernet packet processing.

Experience with cryptographic algorithms and cryptographic solutions for embedded communication systems.

Experience with Mentor Graphics Verification tools.

FPGA/ASIC RTL Design experience.

Proficiency in Object Oriented Programming (C++, JAVA).

Proven proficiency in FPGA/ASIC verification using System Verilog.

Working knowledge of UVM/OVM methodology.

Experience with Advanced Functional Verification tools to report functional coverage.

Experience with scripting languages (Bash, Perl, Python, Tcl).

Familiarity in working within Linux OS.

Familiarity with industry standard interfaces (Ethernet, AXI, SPI).

Solid technical writing skills and ability to communicate complex technical concepts/solutions both inside and outside of the organization.

Highly motivated, self-starter, who works well in team environments.

In compliance with pay transparency requirements, the salary range for this role in New York State is $90,500-$168,500.  The salary range for this role in Maryland is $106,500 - $197,500.  This is not a guarantee of compensation or salary, as final offer amount may vary based on factors including but not limited to experience and geographic location. Our company also offers a variety of benefits, including health and disability insurance, 401(k) match, flexible spending accounts, EAP, education assistance, parental leave, paid time off, and company-paid holidays. The specific programs and options available to an employee may vary depending on date of hire, schedule type, and the applicability of collective bargaining agreements.