Define and refine scalable, reusable testbench architectures that support both simulation-based (UVM) and formal-based verification flows. * Technical Excellence: Drive the adoption of advanced ...
Define and refine scalable, reusable testbench architectures that support both simulation-based (UVM) and formal-based verification flows. * Technical Excellence: Drive the adoption of advanced ...
Define and refine scalable, reusable testbench architectures that support both simulation-based (UVM) and formal-based verification flows. * Technical Excellence: Drive the adoption of advanced ...
Define and refine scalable, reusable testbench architectures that support both simulation-based (UVM) and formal-based verification flows. * Technical Excellence: Drive the adoption of advanced ...
Senior Design Verification Engineer (BO - 01)
Chandler, AZ · On-site
$133K - $163K/yr
Testbench development using UVM methodologies. * Implement functional verification of mixed-signal ASICs. * Failure analysis and resolution, coverage analysis and population. * Digital/mixed-signal ...
Senior Design Verification Engineer (BO - 01)
Chandler, AZ · On-site
$133K - $163K/yr
Testbench development using UVM methodologies. * Implement functional verification of mixed-signal ASICs. * Failure analysis and resolution, coverage analysis and population. * Digital/mixed-signal ...
Principal Engineer
Chandler, AZ · On-site
$160 - $190/hr
Responsible for developing the UVM simulation environment (drivers, monitors, checkers, and assertions) and bridge with mixed signal verification. Develop and run digital and top-level simulations ...
Principal Engineer
Chandler, AZ · On-site
$160 - $190/hr
Responsible for developing the UVM simulation environment (drivers, monitors, checkers, and assertions) and bridge with mixed signal verification. Develop and run digital and top-level simulations ...
Senior Engineer I- Design
Chandler, AZ · On-site
Develop and execute verification plans using UVM/SystemVerilog-based testbenches * Write constrained-random and directed tests to achieve functional and code coverage targets * Apply AI/ML techniques ...
Senior Engineer I- Design
Chandler, AZ · On-site
Develop and execute verification plans using UVM/SystemVerilog-based testbenches * Write constrained-random and directed tests to achieve functional and code coverage targets * Apply AI/ML techniques ...
Staff Engineer, Design Verification Engineering
Chandler, AZ · On-site
$172K - $199K/yr
Architect, implement, and/or manage complete metric-driven SystemVerilog and UVM verification environments as determined by project complexity. SystemVerilog Assertion for Dynamic and Formal ...
Staff Engineer, Design Verification Engineering
Chandler, AZ · On-site
$172K - $199K/yr
Architect, implement, and/or manage complete metric-driven SystemVerilog and UVM verification environments as determined by project complexity. SystemVerilog Assertion for Dynamic and Formal ...
Develop and execute verification plans using UVM/SystemVerilog-based testbenches * Write constrained-random and directed tests to achieve functional and code coverage targets * Apply AI/ML techniques ...
Develop and execute verification plans using UVM/SystemVerilog-based testbenches * Write constrained-random and directed tests to achieve functional and code coverage targets * Apply AI/ML techniques ...
Senior Analog Mixed Signal Verification Engineer
Chandler, AZ · On-site
$140 - $180/hr
Expertise in AMS verification using Verilog-AMS, SystemVerilog, UVM, assertions, mixed-signal simulation, and Real Number Modeling (RNM). Experience developing behavioral models and reusable ...
Senior Analog Mixed Signal Verification Engineer
Chandler, AZ · On-site
$140 - $180/hr
Expertise in AMS verification using Verilog-AMS, SystemVerilog, UVM, assertions, mixed-signal simulation, and Real Number Modeling (RNM). Experience developing behavioral models and reusable ...
Senior Digital Verification Engineer
Chandler, AZ · On-site
$120 - $180/hr
Develop and maintain advanced verification environments using SystemVerilog, UVM, VIPs, scoreboards, monitors, checkers, and assertions. * Create directed and constrained-random test scenarios to ...
Senior Digital Verification Engineer
Chandler, AZ · On-site
$120 - $180/hr
Develop and maintain advanced verification environments using SystemVerilog, UVM, VIPs, scoreboards, monitors, checkers, and assertions. * Create directed and constrained-random test scenarios to ...
Senior Digital Verification Engineer
Chandler, AZ · On-site
$102K - $137K/yr
Develop and maintain advanced verification environments using SystemVerilog, UVM, VIPs, scoreboards, monitors, checkers, and assertions. * Create directed and constrained-random test scenarios to ...
Senior Digital Verification Engineer
Chandler, AZ · On-site
$102K - $137K/yr
Develop and maintain advanced verification environments using SystemVerilog, UVM, VIPs, scoreboards, monitors, checkers, and assertions. * Create directed and constrained-random test scenarios to ...
SystemVerilog/UVM environments * Formal verification where applicable * AMS/DMS co-simulation for mixed-signal validation * Define verification plans that ensure full coverage and sign-off confidence
SystemVerilog/UVM environments * Formal verification where applicable * AMS/DMS co-simulation for mixed-signal validation * Define verification plans that ensure full coverage and sign-off confidence
Senior Analog Mixed Signal Verification Engineer
Chandler, AZ · On-site
$133K/yr
Expertise in AMS verification using Verilog-AMS, SystemVerilog, UVM, assertions, mixed-signal simulation, and Real Number Modeling (RNM). * Experience developing behavioral models and reusable ...
Senior Analog Mixed Signal Verification Engineer
Chandler, AZ · On-site
$133K/yr
Expertise in AMS verification using Verilog-AMS, SystemVerilog, UVM, assertions, mixed-signal simulation, and Real Number Modeling (RNM). * Experience developing behavioral models and reusable ...
SystemVerilog/UVM environments * Formal verification where applicable * AMS/DMS co-simulation for mixed-signal validation * Define verification plans that ensure full coverage and sign-off confidence
Quick apply
SystemVerilog/UVM environments * Formal verification where applicable * AMS/DMS co-simulation for mixed-signal validation * Define verification plans that ensure full coverage and sign-off confidence
Senior Digital Verification Engineer
Chandler, AZ · On-site
$106K - $142K/yr
Develop and maintain advanced verification environments using SystemVerilog, UVM, VIPs, scoreboards, monitors, checkers, and assertions. * Create directed and constrained-random test scenarios to ...
Senior Digital Verification Engineer
Chandler, AZ · On-site
$106K - $142K/yr
Develop and maintain advanced verification environments using SystemVerilog, UVM, VIPs, scoreboards, monitors, checkers, and assertions. * Create directed and constrained-random test scenarios to ...
Staff Engineer, Design Verification Engineering
Chandler, AZ · On-site
$172K - $199K/yr
Architect, implement, and/or manage complete metric-driven SystemVerilog and UVM verification environments as determined by project complexity. SystemVerilog Assertion for Dynamic and Formal ...
Staff Engineer, Design Verification Engineering
Chandler, AZ · On-site
$172K - $199K/yr
Architect, implement, and/or manage complete metric-driven SystemVerilog and UVM verification environments as determined by project complexity. SystemVerilog Assertion for Dynamic and Formal ...
Senior Analog Mixed Signal Verification Engineer
Chandler, AZ · On-site
$138K/yr
Expertise in AMS verification using Verilog-AMS, SystemVerilog, UVM, assertions, mixed-signal simulation, and Real Number Modeling (RNM). * Experience developing behavioral models and reusable ...
Senior Analog Mixed Signal Verification Engineer
Chandler, AZ · On-site
$138K/yr
Expertise in AMS verification using Verilog-AMS, SystemVerilog, UVM, assertions, mixed-signal simulation, and Real Number Modeling (RNM). * Experience developing behavioral models and reusable ...
SystemVerilog/UVM environments * Formal verification where applicable * AMS/DMS co-simulation for mixed-signal validation * Define verification plans that ensure full coverage and sign-off confidence
SystemVerilog/UVM environments * Formal verification where applicable * AMS/DMS co-simulation for mixed-signal validation * Define verification plans that ensure full coverage and sign-off confidence
Senior Staff Mixed Signal Verification Engineer
Chandler, AZ · On-site
$133K/yr
Lead chip-level verification of analog and mixed-signal circuits using AMS and DMS methodologies, integrating analog behavioral models with digital RTL and UVM-based environments. Develop ...
New
Senior Staff Mixed Signal Verification Engineer
Chandler, AZ · On-site
$133K/yr
Lead chip-level verification of analog and mixed-signal circuits using AMS and DMS methodologies, integrating analog behavioral models with digital RTL and UVM-based environments. Develop ...
New
Senior Analog Mixed Signal Verification Engineer
Chandler, AZ · On-site
$133K/yr
Expertise in AMS verification using Verilog-AMS, SystemVerilog, UVM, assertions, mixed-signal simulation, and Real Number Modeling (RNM). * Experience developing behavioral models and reusable ...
Senior Analog Mixed Signal Verification Engineer
Chandler, AZ · On-site
$133K/yr
Expertise in AMS verification using Verilog-AMS, SystemVerilog, UVM, assertions, mixed-signal simulation, and Real Number Modeling (RNM). * Experience developing behavioral models and reusable ...
Senior CPU Design Verification Engineer
Phoenix, AZ · On-site
$135K - $164K/yr
Develop and execute verification plans, testbenches, and SystemVerilog/UVM environments, ensuring comprehensive functional and coverage closure. * Define, run, and analyze systemlevel simulations to ...
Senior CPU Design Verification Engineer
Phoenix, AZ · On-site
$135K - $164K/yr
Develop and execute verification plans, testbenches, and SystemVerilog/UVM environments, ensuring comprehensive functional and coverage closure. * Define, run, and analyze systemlevel simulations to ...
Uvm information
See Arizona salary details
$62.9K - $71.5K
1% of jobs
$71.5K - $80.1K
2% of jobs
$80.1K - $88.7K
5% of jobs
$88.7K - $97.3K
11% of jobs
$100.6K is the 25th percentile. Wages below this are outliers.
$97.3K - $105.9K
16% of jobs
The median wage is $114.2K / yr.
$105.9K - $114.5K
16% of jobs
$114.5K - $123.1K
17% of jobs
$127.9K is the 75th percentile. Wages above this are outliers.
$123.1K - $131.7K
14% of jobs
$131.7K - $140.3K
11% of jobs
$140.3K - $148.9K
5% of jobs
$148.9K - $157.5K
3% of jobs
$62.9K
$116.2K
$157.5K
How much do uvm jobs pay per year?
What is UVM?
What are some common challenges faced by UVM engineers during verification projects?
What are the key skills and qualifications needed to thrive as a UVM employee, and why are they important?
What is the difference between Uvm vs Network Technician?
| Aspect | Uvm | Network Technician |
|---|---|---|
| Required Certifications | UVM certifications, technical training | CompTIA Network+, Cisco CCNA |
| Work Environment | Data centers, server rooms, IT departments | Office settings, client sites, data centers |
| Industry Usage | IT, data management, cloud services | Networking, telecommunications, IT support |
Uvm and Network Technicians both work in IT environments, often requiring similar certifications and working in data centers or network setups. While Uvm specialists focus on virtual machine management and cloud infrastructure, Network Technicians primarily handle network hardware, configurations, and troubleshooting. Both roles are essential in maintaining IT infrastructure but differ in their specific technical focus and daily tasks.
Is UVM a good place to work?
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For Uvm jobs in Arizona, the most frequently searched job titles are:
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The top searched job categories for Uvm jobs in Arizona are:
What cities in Arizona are hiring for Uvm jobs?
Cities in Arizona with the most Uvm job openings:

Full-time
Medical, Retirement
Re-posted 10 days ago
Microchip Technology rating
8.0
Based on 33 frontline employees who took The Breakroom Quiz
59th of 159 rated electronics manufacturers
Job description
People come to work at Microchip because we help design the technology that runs the world. They stay because our culture supports their growth and stability. They are challenged and driven by an incredible array of products and solutions with unlimited career potential. Microchip's nationally-recognized Leadership Passage Programs support career growth where we proudly enroll over a thousand people annually. We take pride in our commitment to employee development, values-based decision making, and strong sense of community, driven by our Vision, Mission, and 11 Guiding Values; we affectionately refer to it as the Aggregate System and it's won us countless awards for diversity and workplace excellence.
Our company is built by dedicated team players who love to challenge the status quo; we did not achieve record revenue and over 30 years of quarterly profitability without a great team dedicated to empowering innovation. People like you.
Visit our careers page to see what exciting opportunities and company perks await!
Job Description:
As the SoC Verification Manager, you will be a critical leader in our dsPIC Microcontroller Business Unit, responsible for ensuring the functional integrity of our next-generation 32-bit MCU products. You will lead, mentor, and scale a high-performing team of 20+ verification engineers to execute complex verification strategies for SoCs featuring ARM and specialized proprietary cores.
Your mission is to drive "First-Pass Silicon Success" by bridging the gap between architectural intent and silicon implementation through cutting-edge UVM and Formal methodologies.
Key Responsibilities
- Strategic Leadership: Own the end-to-end verification strategy, from initial test plan development to final tape-out sign-off for multiple concurrent MCU projects.
- Team Management: Lead and develop a global team of 20+ engineers. Manage resource allocation, performance reviews, and technical career growth.
- Architecture Oversight: Define and refine scalable, reusable testbench architectures that support both simulation-based (UVM) and formal-based verification flows.
- Technical Excellence: Drive the adoption of advanced techniques, including Formal Verification, Power-Aware Verification (UPF/CPF), and Hardware-Software Co-verification.
- Cross-Functional Collaboration: Partner closely with Architecture, RTL Design, Digital Signal Processing (DSP), and Physical Design teams to resolve complex integration issues and architectural bottlenecks.
- Methodology Innovation: Continuously improve verification efficiency through automation, Python/Perl scripting, and the integration of AI-driven verification tools.
Requirements/Qualifications:
Required Qualifications
- Education: Bachelor of Science in Electrical Engineering or Computer Science, with strong digital design fundamentals.
- Experience: 12+ years in SoC Verification, with at least 5 years in a formal leadership or management role.
- Domain Expertise: Proven track record of successful tape-outs for 32-bit Microcontrollers. Deep understanding of MCU peripherals (DMA, Timers, ADC/DAC interfaces, Security modules).
- Processor Knowledge: Direct experience verifying SoCs with ARM cores (Cortex-M) and proprietary RISC-based architectures.
- Methodologies:
- Expert-level command of SystemVerilog and UVM (Universal Verification Methodology).
- Strong hands-on experience with Formal Verification (Property Checking, Connectivity Checking) using tools like JasperGold or VC Formal.
- Protocol Proficiency: In-depth knowledge of AMBA bus protocols (AHB, APB, AXI).
- Verification Infrastructure: Experience defining coverage-driven verification (CDV) metrics and managing massive regression suites. Module level verification plan development, TB plan, TB development and fullchip integration of the module level TB, develop effective functional assertions and coverpoints.
Preferred Skills
- Strong background in Gate-Level Simulations (GLS) and power-aware verification.
- Experience with Post-Silicon Validation, customer support and its alignment with pre-silicon test plans.
- Experience with analog mixed-mode (AMS) simulations.
- Familiarity with functional safety standards (ISO 26262) for automotive MCU applications.
Travel Time:
0% - 25%
Physical Attributes:
Hearing, Seeing, Talking, Works Alone, Works Around Others
Physical Requirements:
sitting 90%
Pay Range:
We offer a total compensation package that ranks among the best in the industry. It consists of competitive base pay, restricted stock units, and quarterly bonus payments. In addition to these components, our package includes health benefits that begin day one, retirement savings plans, and an industry leading ESPP program with a 2 year look back feature. Find more information about all our benefits at the link below:
Benefits of working at Microchip
The annual base salary range for this position, which could be performed in the US, is $91,000 - $247,000.*
*Range is dependent on numerous factors including job location, skills and experience.
Microchip Technology Inc is an equal opportunity/affirmative action employer. All qualified applicants will receive consideration for employment without regard to sex, gender identity, sexual orientation, race, color, religion, national origin, disability, protected Veteran status, age, or any other characteristic protected by law.
For more information on applicable equal employment regulations, please refer to the Know Your Rights: Workplace Discrimination is Illegal Poster.
To all recruitment agencies: Microchip Technology Inc. does not accept unsolicited agency resumes. Please do not forward resumes to our recruiting team or other Microchip employees. Microchip is not responsible for any fees related to unsolicited resumes.
What Microchip Technology employees say
Pay
Benefits
Hours and flexibility
Workplace
Get the full story on Breakroom
About Microchip
Sourced by ZipRecruiter
Industry
It services
Company size
10,000+ Employees
Headquarters location
Chandler, AZ, US
Year founded
1989