Senior Design Verification Engineer
$176K - $264K/yr
Testbench development using SystemVerilog/UVM * Hands-on debug with the design team * Ensuring quality via collection and analysis of coverage metrics including code and functional coverage
Senior Design Verification Engineer
$176K - $264K/yr
Testbench development using SystemVerilog/UVM * Hands-on debug with the design team * Ensuring quality via collection and analysis of coverage metrics including code and functional coverage
Senior Design Verification Engineer with Security Clearance
Tempe, AZ · On-site
$176K - $264K/yr
Testbench development using SystemVerilog/UVM * Hands-on debug with the design team * Ensuring quality via collection and analysis of coverage metrics including code and functional coverage
Senior Design Verification Engineer with Security Clearance
Tempe, AZ · On-site
$176K - $264K/yr
Testbench development using SystemVerilog/UVM * Hands-on debug with the design team * Ensuring quality via collection and analysis of coverage metrics including code and functional coverage
Senior Design Verification Engineer
Tempe, AZ · On-site
$176K - $264K/yr
Testbench development using SystemVerilog/UVM * Hands-on debug with the design team * Ensuring quality via collection and analysis of coverage metrics including code and functional coverage
Senior Design Verification Engineer
Tempe, AZ · On-site
$176K - $264K/yr
Testbench development using SystemVerilog/UVM * Hands-on debug with the design team * Ensuring quality via collection and analysis of coverage metrics including code and functional coverage
Advanced ASIC FPGA Verification Engineer for Crypto and Cross Domain Solutions
Scottsdale, AZ · On-site
$135K - $150K/yr
Take ownership, lead, develop and maintain UVM-based and non-UVM-based verification environments for complex FPGA designs including cryptographic engines, protocol interfaces, and system-level ...
Advanced ASIC FPGA Verification Engineer for Crypto and Cross Domain Solutions
Scottsdale, AZ · On-site
$135K - $150K/yr
Take ownership, lead, develop and maintain UVM-based and non-UVM-based verification environments for complex FPGA designs including cryptographic engines, protocol interfaces, and system-level ...
Senior Technical Staff Engineer - Verification
$133K - $163K/yr
Architect, develop, and maintain UVM verification environments and Formal verification environments. * Define verification plans and implement constrained-random UVM Testbench and/or Formal Testbench.
Senior Technical Staff Engineer - Verification
$133K - $163K/yr
Architect, develop, and maintain UVM verification environments and Formal verification environments. * Define verification plans and implement constrained-random UVM Testbench and/or Formal Testbench.
Senior Technical Staff Engineer - Verification
Chandler, AZ · On-site
$133K - $163K/yr
Architect, develop, and maintain UVM verification environments and Formal verification environments. * Define verification plans and implement constrained-random UVM Testbench and/or Formal Testbench.
Senior Technical Staff Engineer - Verification
Chandler, AZ · On-site
$133K - $163K/yr
Architect, develop, and maintain UVM verification environments and Formal verification environments. * Define verification plans and implement constrained-random UVM Testbench and/or Formal Testbench.
Take ownership, lead, develop and maintain UVM-based and non-UVM-based verification environments for complex FPGA designs including cryptographic engines, protocol interfaces, and system-level ...
Take ownership, lead, develop and maintain UVM-based and non-UVM-based verification environments for complex FPGA designs including cryptographic engines, protocol interfaces, and system-level ...
Analog Mixed Signal Modeling Engineer (UL - 02)
Chandler, AZ · On-site
$198K/yr
Collaborate with UVM verification engineers to ensure all verification components are used for AMS-UVM flow * Contribute to development of automation tools for design, verification and modeling ...
Analog Mixed Signal Modeling Engineer (UL - 02)
Chandler, AZ · On-site
$198K/yr
Collaborate with UVM verification engineers to ensure all verification components are used for AMS-UVM flow * Contribute to development of automation tools for design, verification and modeling ...
FPGA Embedded Engineer with Security Clearance
Tucson, AZ · On-site
$116K - $149K/yr
... UVM using System Verilog • Verification utilizing emulation platforms, such as Veloce
FPGA Embedded Engineer with Security Clearance
Tucson, AZ · On-site
$116K - $149K/yr
... UVM using System Verilog • Verification utilizing emulation platforms, such as Veloce
FPGA Engineer with Security Clearance
Tucson, AZ · On-site
$113K - $156K/yr
... UVM using System Verilog • Verification utilizing emulation platforms, such as Veloce
FPGA Engineer with Security Clearance
Tucson, AZ · On-site
$113K - $156K/yr
... UVM using System Verilog • Verification utilizing emulation platforms, such as Veloce
FPGA Engineer with Security Clearance
Tucson, AZ · On-site
$114K - $157K/yr
... UVM using System Verilog • Verification utilizing emulation platforms, such as Veloce
FPGA Engineer with Security Clearance
Tucson, AZ · On-site
$114K - $157K/yr
... UVM using System Verilog • Verification utilizing emulation platforms, such as Veloce
FPGA Engineer
Tucson, AZ · On-site
$122K - $157K/yr
... UVM using System Verilog • Verification utilizing emulation platforms, such as Veloce #CJ
FPGA Engineer
Tucson, AZ · On-site
$122K - $157K/yr
... UVM using System Verilog • Verification utilizing emulation platforms, such as Veloce #CJ
Design Verification Engineer
Chandler, AZ · On-site
$133K - $163K/yr
Design and implement UVM-based testbenches, including infrastructure, scoreboards, checkers, and assertions. * Create directed and constrained-random test suites to ensure robust functional coverage.
Design Verification Engineer
Chandler, AZ · On-site
$133K - $163K/yr
Design and implement UVM-based testbenches, including infrastructure, scoreboards, checkers, and assertions. * Create directed and constrained-random test suites to ensure robust functional coverage.
Senior Design Verification Engineer
Chandler, AZ · On-site
$133K - $163K/yr
Design and implement UVM-based testbenches, including infrastructure, scoreboards, checkers, and assertions. * Create directed and constrained-random test suites to ensure robust functional coverage.
Senior Design Verification Engineer
Chandler, AZ · On-site
$133K - $163K/yr
Design and implement UVM-based testbenches, including infrastructure, scoreboards, checkers, and assertions. * Create directed and constrained-random test suites to ensure robust functional coverage.
Senior Staff Design Verification Engineer
Chandler, AZ · On-site
$133K - $163K/yr
Design and implement UVM-based testbenches, including infrastructure, scoreboards, checkers, and assertions. * Create directed and constrained-random test suites to ensure robust functional coverage.
Senior Staff Design Verification Engineer
Chandler, AZ · On-site
$133K - $163K/yr
Design and implement UVM-based testbenches, including infrastructure, scoreboards, checkers, and assertions. * Create directed and constrained-random test suites to ensure robust functional coverage.
Digital Design Verification Engineer | Precision ADC
Tucson, AZ · On-site
$116K - $142K/yr
In this position, you will develop SystemVerilog/UVM testbenches to verify the digital logic, calibration algorithms, and mixed-signal interfaces of Signal chains involving high-resolution delta ...
Digital Design Verification Engineer | Precision ADC
Tucson, AZ · On-site
$116K - $142K/yr
In this position, you will develop SystemVerilog/UVM testbenches to verify the digital logic, calibration algorithms, and mixed-signal interfaces of Signal chains involving high-resolution delta ...
Staff Design Verification Engineer
Chandler, AZ · On-site
$133K - $163K/yr
Design and implement UVM-based testbenches, including infrastructure, scoreboards, checkers, and assertions. * Create directed and constrained-random test suites to ensure robust functional coverage.
Staff Design Verification Engineer
Chandler, AZ · On-site
$133K - $163K/yr
Design and implement UVM-based testbenches, including infrastructure, scoreboards, checkers, and assertions. * Create directed and constrained-random test suites to ensure robust functional coverage.
Define and refine scalable, reusable testbench architectures that support both simulation-based (UVM) and formal-based verification flows. * Technical Excellence: Drive the adoption of advanced ...
Define and refine scalable, reusable testbench architectures that support both simulation-based (UVM) and formal-based verification flows. * Technical Excellence: Drive the adoption of advanced ...
Define and refine scalable, reusable testbench architectures that support both simulation-based (UVM) and formal-based verification flows. * Technical Excellence: Drive the adoption of advanced ...
Define and refine scalable, reusable testbench architectures that support both simulation-based (UVM) and formal-based verification flows. * Technical Excellence: Drive the adoption of advanced ...
Digital Design Verification Engineer | Precision ADC
$116K - $142K/yr
In this position, you will develop SystemVerilog/UVM testbenches to verify the digital logic, calibration algorithms, and mixed-signal interfaces of Signal chains involving high-resolution delta ...
Digital Design Verification Engineer | Precision ADC
$116K - $142K/yr
In this position, you will develop SystemVerilog/UVM testbenches to verify the digital logic, calibration algorithms, and mixed-signal interfaces of Signal chains involving high-resolution delta ...
Uvm information
See Arizona salary details
$62.9K - $71.5K
1% of jobs
$71.5K - $80.1K
2% of jobs
$80.1K - $88.7K
5% of jobs
$88.7K - $97.3K
11% of jobs
$100.6K is the 25th percentile. Wages below this are outliers.
$97.3K - $105.9K
16% of jobs
The median wage is $114.2K / yr.
$105.9K - $114.5K
16% of jobs
$114.5K - $123.1K
17% of jobs
$127.9K is the 75th percentile. Wages above this are outliers.
$123.1K - $131.7K
14% of jobs
$131.7K - $140.3K
11% of jobs
$140.3K - $148.9K
5% of jobs
$148.9K - $157.5K
3% of jobs
$62.9K
$116.2K
$157.5K
How much do uvm jobs pay per year?
As of Jul 30, 2026, the average yearly pay for uvm in Arizona is $116,228.00, according to ZipRecruiter salary data. Most workers in this role earn between $100,200.00 and $130,500.00 per year, depending on experience, location, and employer.
What is the difference between Uvm vs Network Technician?
| Aspect | Uvm | Network Technician |
|---|---|---|
| Required Certifications | UVM certifications, technical training | CompTIA Network+, Cisco CCNA |
| Work Environment | Data centers, server rooms, IT departments | Office settings, client sites, data centers |
| Industry Usage | IT, data management, cloud services | Networking, telecommunications, IT support |
Uvm and Network Technicians both work in IT environments, often requiring similar certifications and working in data centers or network setups. While Uvm specialists focus on virtual machine management and cloud infrastructure, Network Technicians primarily handle network hardware, configurations, and troubleshooting. Both roles are essential in maintaining IT infrastructure but differ in their specific technical focus and daily tasks.
What are some common challenges faced by UVM (Universal Verification Methodology) engineers during verification projects?
UVM engineers often encounter challenges such as managing complex testbenches, ensuring comprehensive coverage, and debugging intricate design issues. Coordinating with design and RTL teams to clarify specifications and resolve inconsistencies can also be demanding. Additionally, maintaining reusable and scalable verification environments requires strong coding practices and continuous learning, especially as projects evolve in size and complexity. Collaborating effectively across cross-functional teams is essential to ensure timely project completion.
What are UVMs in the context of job titles?
UVM stands for Universal Verification Methodology, which is a standardized methodology used in the semiconductor industry for verifying integrated circuit designs. UVM engineers or verification engineers use this approach to develop reusable testbenches and improve the efficiency and accuracy of hardware verification. Their responsibilities typically include creating test environments, writing tests in SystemVerilog, and ensuring that chip designs work as intended before manufacturing.
What are the key skills and qualifications needed to thrive as a uvm (University of Vermont) employee, and why are they important?
To excel as a University of Vermont (UVM) employee, you generally need a relevant educational background and expertise specific to your department or position, such as teaching, research, or administration. Familiarity with academic software, campus management systems, and relevant certifications (e.g., teaching credentials or research compliance) is often required. Strong communication, collaboration, and adaptability are essential soft skills for engaging with students, colleagues, and the broader academic community. These skills and qualifications are vital for fostering an effective, innovative, and supportive university environment.
What are popular job titles related to Uvm jobs in Arizona? For Uvm jobs in Arizona, the most frequently searched job titles are:
What job categories do people searching Uvm jobs in Arizona look for? The top searched job categories for Uvm jobs in Arizona are:
What cities in Arizona are hiring for Uvm jobs? Cities in Arizona with the most Uvm job openings:
$176K - $264K/yr
Full-time
Re-posted 21 days ago
Viasat rating
6.3
Based on 11 frontline employees who took The Breakroom Quiz
79th of 96 rated telecommunications companies
Job description
About us
What you'll do
The day-to-day
What you'll need
What will help you on the job
Salary range
$141,500.00 - $224,000.00 / annually.For specific work locations within San Jose, the San Francisco Bay area and New York City metropolitan area, the base pay range for this role is $176,000.00- $264,000.00/ annually
At Viasat, we consider many factors when it comes to compensation, including the scope of the position as well as your background and experience. Base pay may vary depending on job-related knowledge, skills, and experience. Additional cash or stock incentives may be provided as part of the compensation package, in addition to a range of medical, financial, and/or other benefits, dependent on the position offered. Learn more about Viasat's comprehensive benefit offerings that are focused on your holistic health and wellness at https://careers.viasat.com/benefits.
EEO Statement
One team. Global challenges. Infinite opportunities. At Viasat, we’re on a mission to deliver connections with the capacity to change the world. For more than 35 years, Viasat has helped shape how consumers, businesses, governments and militaries around the globe communicate. We’re looking for people who think big, act fearlessly, and create an inclusive environment that drives positive impact to join our team.
What you'll do
At Viasat, you will be joining a talented and motivated team of systems engineers, design engineers, and design verification engineers developing cutting edge communications technology with a focus on high quality and time to market.
You will be working in a verification environment utilizing current tools and methodologies such as Universal Verification Methodology (UVM) and new DV AI agentic tools. You will be asked to help evaluate and deploy new technologies for design verification as they become available.
As a Design Verification Engineer, you will be part of a verification team responsible for the full cycle of RTL verification for FPGA and ASIC designs. You will be responsible for:
- Design verification planning including test plans
- Testbench development using SystemVerilog/UVM
- Hands-on debug with the design team
- Ensuring quality via collection and analysis of coverage metrics including code and functional coverage
- Managing regressions and compute resources
- Tool evaluation and license management
- Responsible for owning and driving technical issues to resolution
The day-to-day
Architecting Design Verification environments for ASICs and FPGAs.
Working with RTL, System and software engineers to determine appropriate coverage closure for chip designs.
Create drivers, monitors, scoreboards, sequences, and model predictors for a variety of interfaces and designs.
Maintaining and communicating program schedule and task tracking (Agile Jira based).
Debugging failing tests, understanding both the UVM testbench and VHDL/Verilog source code, working closely with the RTL developers.
What you'll need
- 8+ years Design Verification experience including UVM experience
Experience in UVM testbench creation and usage
Bachelor's Degree in Electrical Engineering, Computer Engineering or a related field
Experience with AI and agentic flow methodologies for design verification and chip development
Foundational knowledge of digital logic and timing considerations
Attention to detail, ability to follow process and coding guidelines, participate in code reviews and accept feedback
Experience with industry standard simulators such as Questa, Xcelium and VCS
Proven track record of work in UVM testbench development
US citizenship
Ability to travel up to 10%
- Must be able to obtain a secret clearance
What will help you on the job
Strong written and verbal communication skills, ability to work with a geographically distributed team
Object oriented programming experience
Familiarity with designing and coding for testbench horizontal and vertical re-use
Familiarity with AI coding agents for design verificaiton
Ability to work independently, take initiative, and take ownership of tasks and results
#LI-AF1
Salary range
$141,500.00 - $224,000.00 / annually.For specific work locations within San Jose, the San Francisco Bay area and New York City metropolitan area, the base pay range for this role is $176,000.00- $264,000.00/ annually
At Viasat, we consider many factors when it comes to compensation, including the scope of the position as well as your background and experience. Base pay may vary depending on job-related knowledge, skills, and experience. Additional cash or stock incentives may be provided as part of the compensation package, in addition to a range of medical, financial, and/or other benefits, dependent on the position offered. Learn more about Viasat's comprehensive benefit offerings that are focused on your holistic health and wellness at https://careers.viasat.com/benefits.
EEO Statement
Viasat is proud to be an equal opportunity employer, seeking to create a welcoming and diverse environment. All qualified applicants will receive consideration for employment without regard to race, color, religion, gender, gender identity or expression, sexual orientation, national origin, ancestry, physical or mental disability, medical condition, marital status, genetics, age, or veteran status or any other applicable legally protected status or characteristic. If you would like to request an accommodation on the basis of disability for completing this on-line application, please click here.
Qualifications:- 8+ years Design Verification experience including UVM experience
Experience in UVM testbench creation and usage
Bachelor's Degree in Electrical Engineering, Computer Engineering or a related field
Experience with AI and agentic flow methodologies for design verification and chip development
Foundational knowledge of digital logic and timing considerations
Attention to detail, ability to follow process and coding guidelines, participate in code reviews and accept feedback
Experience with industry standard simulators such as Questa, Xcelium and VCS
Proven track record of work in UVM testbench development
US citizenship
Ability to travel up to 10%
- Must be able to obtain a secret clearance
About ViaSat
Sourced by ZipRecruiter
At Viasat, we're on a mission to deliver connections with the capacity to change the world. For more than 35 years, Viasat has helped shape how consumers, businesses, governments and militaries around the globe communicate.
Industry
Telecommunications
Company size
5,001 - 10,000 Employees
Headquarters location
Carlsbad, CA, US
Year founded
1986