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Temporary Asic Rtl Design Engineer Jobs in Massachusetts

You'll work on cutting-edge ASIC and FPGA solutions, collaborating closely with cross-functional ... Write and verify RTL code for high-performance hardware components. * Support hardware bring-up and ...

As an ASIC STA Engineer, you will have responsibilities spanning all aspects of SoC design in terms ... You will closely interact with RTL designer to understand design intent and clock structure, with ...

As an ASIC STA Engineer, you will have responsibilities spanning all aspects of SoC design in terms ... You will closely interact with RTL designer to understand design intent and clock structure, with ...

As a logic design engineer, you will be involved in all phases of the design, from concept study ... You will provide high-quality RTL description, including assertions, for the design. Use formal ...

As a logic design engineer, you will be involved in all phases of the design, from concept study ... You will provide high-quality RTL description, including assertions, for the design. Use formal ...

We are looking for an ASIC Implementation Engineer with demonstrated expertise in multiple disciplines including synthesis, design for test, floorplanning, place and route, clock methodology, power ...

FPGA Design Engineer Staff

Andover, MA · On-site

$124K - $171K/yr

You will be the ASIC & FPGA Design Engineer for the Andover, MA Advanced Defense Systems team. Our ... Defining FPGA architecture, writing RTL (VHDL/Verilog/SystemVerilog), and producing complete design ...

We are looking for an ASIC Implementation Engineer with demonstrated expertise in multiple disciplines including synthesis, design for test, floorplanning, place and route, clock methodology, power ...

Description As an ASIC STA Engineer, you will have responsibilities spanning all aspects of SoC ... You will closely interact with RTL designer to understand design intent and clock structure, with ...

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Temporary Asic Rtl Design Engineer information

What is the difference between Temporary Asic Rtl Design Engineer vs Temporary FPGA Design Engineer?

AspectTemporary Asic Rtl Design EngineerTemporary FPGA Design Engineer
Primary FocusDesigning RTL code for ASIC chipsDesigning FPGA logic and configurations
Skills & CertificationsVerilog/VHDL, ASIC design flow, simulation toolsVerilog/VHDL, FPGA development tools, synthesis
Work EnvironmentSemiconductor companies, ASIC design teamsFPGA development labs, prototyping environments
Industry UsageUsed in high-volume chip manufacturingUsed for prototyping, testing, and low-volume products

Both roles involve RTL design using Verilog or VHDL, but the Temporary Asic Rtl Design Engineer focuses on ASIC chip development, while the Temporary FPGA Design Engineer specializes in FPGA-based prototyping and testing. The choice depends on whether the project aims for mass production or flexible, rapid development.

What are the most commonly searched types of Asic Rtl Design Engineer jobs in Massachusetts? The most popular types of Asic Rtl Design Engineer jobs in Massachusetts are:
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What cities in Massachusetts are hiring for Temporary Asic Rtl Design Engineer jobs? Cities in Massachusetts with the most Temporary Asic Rtl Design Engineer job openings:
Staff Engineer, Digital ASIC Design (CONTRACT)

Staff Engineer, Digital ASIC Design (CONTRACT)

Butterfly Network

Burlington, MA • On-site

$148K/yr

Temporary

Posted 16 days ago


Job description

Job Description
The role of the Staff Digital ASIC Designer offers the opportunity to work within the heart of the product development team and founders and to own the core of what will set Butterfly Network apart. This individual will design, implement, and verify digital signal processing, high speed interface, and system-on-a-chip logic for a suite of next-generation products.
As part of our team, your core responsibilities will be:
  • Develop low-power RTL for large SoCs in an advanced node.
  • Implement and optimize signal processing algorithms in RTL.
  • Integrate multiple embedded processor cores into a large design.
  • Develop efficient high bandwidth on chip data paths.
  • Other Technology, Architecture, & Productivity duties as assigned

Qualifications
Baseline skills/experiences/attributes:
  • BS/MS/PhD in EE/CE (or equivalent practical silicon design experience).
  • 8+ years (typical Staff level) in digital IC / ASIC / SoC design with substantial hands-on RTL ownership and at least one major-IP or full-chip tapeout cycle.
  • Proven ownership of a defined digital IP/subsystem from micro-architecture and RTL implementation through verification closure and tapeout support.
  • Strong RTL skills in SystemVerilog/Verilog, including pipelined datapaths, control logic/state machines, and high-throughput streaming interfaces.
  • Experience designing sustained high-throughput datapaths, including buffering/FIFOs, arbitration/backpressure, bandwidth budgeting, and SRAM/memory interface considerations.
  • Strong understanding of silicon-level design constraints, including clock/reset architecture, CDC/RDC risk mitigation, power-aware design, and PPA tradeoffs.
  • Effective collaboration with verification to drive functional closure through signoff (SV/UVM and/or Python-based frameworks such as cocotb).
  • Experience building and using bit-accurate reference models (e.g., Python) to validate fixed-point behavior and enable end-to-end checking.
  • Experience supporting post-silicon bring-up/debug and silicon correlation, partnering with firmware/validation to root-cause issues and deliver fixes.
  • Strong cross-functional communication to close hardware-firmware interfaces (register maps, control/status paths, data-plane contracts) with systems/firmware stakeholders.

Ideally, you also have these skills/experiences/attributes (but it's ok if you don't!):
  • Experience implementing compute-intensive DSP pipelines (e.g., beamforming, filtering, noise reduction, MAC-heavy datapaths) with fixed-point design discipline.
  • Exposure to ultrasound / medical imaging systems or sensor data acquisition pipelines and image-quality KPIs.
  • Advanced-node experience (28nm or smaller), including timing sensitivity and third-party IP integration.
  • (Optional, only if this matches the role) Experience integrating programmable compute subsystems (MPU/accelerator), including control interfaces and memory/bandwidth tradeoffs.

Values
Innovation is what we do. Our values are how we make it happen. Butterflies are and believe in...
  • Patient-Centric Innovators: Our mission is THE mission.
  • Empowered to Impact: Every voice matters.
  • One Team, One Goal: Unity fuels progress.
  • Growth Champions: We embrace challenges.
  • Action-Oriented Achievers: We follow through, every time.

Location
Butterfly offers a hybrid work model for most positions, with team members spending two or more days a week in the office. While flexibility is key, we value in-person connections that spark creativity and teamwork. Our offices are designed for collaboration, with comfortable workspaces, stocked kitchens, and opportunities to connect with peers.
This is a hybrid position and will be based out of our office in either the Greater SF Bay Area or Burlington, MA.
For this temporary role, we are only considering candidates who are legally authorized to work in the United States and who do not now or in the future require sponsorship or transfer for employment visa status.
Butterfly network does not accept agency resumes for this temporary position.
Butterfly Network Inc. is an E-Verify Company and is an equal opportunity employer regardless of race, color, ancestry, religion, gender, national origin, sexual orientation, age, citizenship, marital status, disability or Veteran status. All your information will be kept confidential according to EEO guidelines.
Butterfly requires security adherence responsibilities from all employees. These include: adhering to all company security policies and procedures, utilize provided company assets securely, and complete all required security awareness training programs. Safeguarding company data and systems from unauthorized access, modification, or