Santa Clara, CA · On-site
$175K/yr
The ideal candidate has hands-on experience across the full ASIC development cycle - from RTL ... We are seeking a Senior ASIC Design Engineer with seasonedexperience in the development of high ...
Santa Clara, CA · On-site
$175K/yr
The ideal candidate has hands-on experience across the full ASIC development cycle - from RTL ... We are seeking a Senior ASIC Design Engineer with seasonedexperience in the development of high ...
San Jose, CA · On-site
$150K - $275K/yr
Job Summary As an RTL Engineer at Etched, you will be critical in ensuring that our AI chips ... both our existing and upcoming ASIC designs. In this role, you will work closely with ...
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San Jose, CA · On-site
$150K - $275K/yr
Job Summary As an RTL Engineer at Etched, you will be critical in ensuring that our AI chips ... both our existing and upcoming ASIC designs. In this role, you will work closely with ...
Irvine, CA · On-site
$140K - $175K/yr
RTL DESIGN ENGINEER (SILICON ENGINEERING) At SpaceX we're leveraging our experience in building ... Participate in the full ASIC/FPGA design lifecycle for Starlink projects, from high-level ...
Irvine, CA · On-site
$140K - $175K/yr
RTL DESIGN ENGINEER (SILICON ENGINEERING) At SpaceX we're leveraging our experience in building ... Participate in the full ASIC/FPGA design lifecycle for Starlink projects, from high-level ...
Engineering Group, Engineering Group > ASICS Engineering General Summary: Role: As a Design ... Experience: 10+ years of ASIC design experience * RTL Expertise: System Verilog Design, Linting ...
Engineering Group, Engineering Group > ASICS Engineering General Summary: Role: As a Design ... Experience: 10+ years of ASIC design experience * RTL Expertise: System Verilog Design, Linting ...
San Jose, CA · On-site
$150K - $275K/yr
Job Summary As an RTL Engineer at Etched, you will be critical in ensuring that our AI chips ... both our existing and upcoming ASIC designs. In this role, you will work closely with ...
San Jose, CA · On-site
$150K - $275K/yr
Job Summary As an RTL Engineer at Etched, you will be critical in ensuring that our AI chips ... both our existing and upcoming ASIC designs. In this role, you will work closely with ...
$147.40K - $272.10K/yr
... RTL designs - Working with design verification and formal verification teams to verify ... front-end ASIC RTL design Tight-knit collaboration skills with excellent written and verbal ...
$147.40K - $272.10K/yr
... RTL designs - Working with design verification and formal verification teams to verify ... front-end ASIC RTL design Tight-knit collaboration skills with excellent written and verbal ...
Cupertino, CA · On-site
$126.80K - $190.90K/yr
... RTL designs - Working with design verification and formal verification teams to verify ... front-end ASIC RTL design Tight-knit collaboration skills with excellent written and verbal ...
Cupertino, CA · On-site
$126.80K - $190.90K/yr
... RTL designs - Working with design verification and formal verification teams to verify ... front-end ASIC RTL design Tight-knit collaboration skills with excellent written and verbal ...
... building RTL designs- Working with design verification and formal verification teams to verify ... front-end ASIC RTL designTight-knit collaboration skills with excellent written and verbal ...
... building RTL designs- Working with design verification and formal verification teams to verify ... front-end ASIC RTL designTight-knit collaboration skills with excellent written and verbal ...
... building RTL designs- Working with design verification and formal verification teams to verify ... front-end ASIC RTL designTight-knit collaboration skills with excellent written and verbal ...
... building RTL designs- Working with design verification and formal verification teams to verify ... front-end ASIC RTL designTight-knit collaboration skills with excellent written and verbal ...
$120K - $225K/yr
We're hiring experienced RTL Design Engineers from junior to senior levels to play a key role in designing and implementing the components that will bring our next-generation AI processors to life.
$120K - $225K/yr
We're hiring experienced RTL Design Engineers from junior to senior levels to play a key role in designing and implementing the components that will bring our next-generation AI processors to life.
... building RTL designs- Working with design verification and formal verification teams to verify ... front-end ASIC RTL designTight-knit collaboration skills with excellent written and verbal ...
... building RTL designs- Working with design verification and formal verification teams to verify ... front-end ASIC RTL designTight-knit collaboration skills with excellent written and verbal ...
NVIDIA is seeking ASIC Design Engineers to implement the world's leading SoC's and GPU's. This ... Craft micro-architecture, implement in RTL, and deliver a fully verified, synthesis/timing clean ...
NVIDIA is seeking ASIC Design Engineers to implement the world's leading SoC's and GPU's. This ... Craft micro-architecture, implement in RTL, and deliver a fully verified, synthesis/timing clean ...
$120K - $225K/yr
We're hiring experienced RTL Design Engineers from junior to senior levels to play a key role in designing and implementing the components that will bring our next-generation AI processors to life.
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$120K - $225K/yr
We're hiring experienced RTL Design Engineers from junior to senior levels to play a key role in designing and implementing the components that will bring our next-generation AI processors to life.
$181.10K - $318.40K/yr
... RTL designs - Working with design verification and formal verification teams to verify ... front-end ASIC RTL design Tight-knit collaboration skills with excellent written and verbal ...
$181.10K - $318.40K/yr
... RTL designs - Working with design verification and formal verification teams to verify ... front-end ASIC RTL design Tight-knit collaboration skills with excellent written and verbal ...
NVIDIA is seeking ASIC Design Engineers to implement the world's leading SoC's and GPU's. This ... Craft micro-architecture, implement in RTL, and deliver a fully verified, synthesis/timing clean ...
NVIDIA is seeking ASIC Design Engineers to implement the world's leading SoC's and GPU's. This ... Craft micro-architecture, implement in RTL, and deliver a fully verified, synthesis/timing clean ...
Santa Clara, CA · Hybrid
Role: (RTL) Design Engineer Location: Santa Clara, CA (Hybrid negotiable) Interview: Phone/Skype We're looking for a seasoned RTL engineer with 7+ years of experience in #RTLDesign #Verilog #VLSI ...
Santa Clara, CA · Hybrid
Role: (RTL) Design Engineer Location: Santa Clara, CA (Hybrid negotiable) Interview: Phone/Skype We're looking for a seasoned RTL engineer with 7+ years of experience in #RTLDesign #Verilog #VLSI ...
Santa Clara, CA · On-site
Role: (RTL) Design Engineer Location: Santa Clara, CA (Hybrid negotiable) Interview: Phone/Skype We're looking for a seasoned RTL engineer with 7+ years of experience in #RTLDesign #Verilog #VLSI ...
Santa Clara, CA · On-site
Role: (RTL) Design Engineer Location: Santa Clara, CA (Hybrid negotiable) Interview: Phone/Skype We're looking for a seasoned RTL engineer with 7+ years of experience in #RTLDesign #Verilog #VLSI ...
Job Title: RTL Design Engineer Location: San Jose, CA (Onsite) Mode: Contract (6+ Months) Key ... Experience with all aspects of the SoC/ASIC design, verification, and implementation flow * Work ...
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Job Title: RTL Design Engineer Location: San Jose, CA (Onsite) Mode: Contract (6+ Months) Key ... Experience with all aspects of the SoC/ASIC design, verification, and implementation flow * Work ...
San Jose, CA · On-site
$180K - $210K/yr
About the Role As a Principal ASIC Design Engineer, you will be responsible for all aspects of ... Develop functional tests/testbenches and run RTL and gate-level simulations. * Work with ...
San Jose, CA · On-site
$180K - $210K/yr
About the Role As a Principal ASIC Design Engineer, you will be responsible for all aspects of ... Develop functional tests/testbenches and run RTL and gate-level simulations. * Work with ...
About the Role As a Principal ASIC Design Engineer, you will be responsible for all aspects of ... Develop functional tests/testbenches and run RTL and gate-level simulations. * Work with ...
Quick apply
About the Role As a Principal ASIC Design Engineer, you will be responsible for all aspects of ... Develop functional tests/testbenches and run RTL and gate-level simulations. * Work with ...
| Aspect | Temporary Asic Rtl Design Engineer | Temporary FPGA Design Engineer |
|---|---|---|
| Primary Focus | Designing RTL code for ASIC chips | Designing FPGA logic and configurations |
| Skills & Certifications | Verilog/VHDL, ASIC design flow, simulation tools | Verilog/VHDL, FPGA development tools, synthesis |
| Work Environment | Semiconductor companies, ASIC design teams | FPGA development labs, prototyping environments |
| Industry Usage | Used in high-volume chip manufacturing | Used for prototyping, testing, and low-volume products |
Both roles involve RTL design using Verilog or VHDL, but the Temporary Asic Rtl Design Engineer focuses on ASIC chip development, while the Temporary FPGA Design Engineer specializes in FPGA-based prototyping and testing. The choice depends on whether the project aims for mass production or flexible, rapid development.
Santa Clara, CA • On-site
$175K/yr
Full-time
Posted 28 days ago
7.8
Based on 6 frontline employees who took The Breakroom Quiz
53rd of 137 rated electronics manufacturers
Sourced by ZipRecruiter
Computer and electronic product manufacturing
5,001 - 10,000 Employees
Sunnyvale, CA, US
1969
