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Temporary Asic Rtl Design Engineer Jobs in California

RTL Design Engineer

San Jose, CA · On-site

$150K - $275K/yr

Job Summary As an RTL Engineer at Etched, you will be critical in ensuring that our AI chips ... both our existing and upcoming ASIC designs. In this role, you will work closely with ...

Lead RTL Design Engineer

Sunnyvale, CA · Hybrid

$175K - $275K/yr

About The Role As a lead front-end design engineer, you will be a key part of the world-class team ... The role also requires close collaboration and management of external ASIC vendor. You will ...

... ASIC design. * Experience interacting with software, system hardware, and other cross-functional ... You will design RTL Intellectual Property (IP) with the focus on management and control subsystem ...

ASIC Engineer

San Jose, CA · On-site

$194K/yr

ASIC Engineer Location: San Jose, CA Duration: 6 Months Minimum Required Skills ... ASIC Design, FPGA, RTL Design, Chip Architecture, ASIC, Implementation,Synthesis /Conformal ...

RTL Design Engineer

San Jose, CA · On-site

$150K - $275K/yr

Job Summary As an RTL Engineer at Etched, you will be critical in ensuring that our AI chips ... both our existing and upcoming ASIC designs. In this role, you will work closely with ...

ASIC/SOC power engineers with experience on tools like PTPX / RTL-A. • We are seeking a highly skilled and motivated Contract Worker for RTL Design and Verification with expertise in power ...

We're hiring experienced RTL Design Engineers from junior to senior levels to play a key role in designing and implementing the components that will bring our next-generation AI processors to life.

Position: RTL Design Engineers Type: Contract Compensation: $100-$175/hour Location: Remote ... Experience with ASIC design flows and common EDA tools . * Ability to write clear design ...

NVIDIA is seeking ASIC Design Engineers to implement the world's leading SoC's and GPU's. This ... Craft micro-architecture, implement in RTL, and deliver a fully verified, synthesis/timing clean ...

We're hiring experienced RTL Design Engineers from junior to senior levels to play a key role in designing and implementing the components that will bring our next-generation AI processors to life.

RTL Design Engineer

Palo Alto, CA · On-site

$120K - $225K/yr

We're hiring experienced RTL Design Engineers from junior to senior levels to play a key role in designing and implementing the components that will bring our next-generation AI processors to life.

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Temporary Asic Rtl Design Engineer information

What is the difference between Temporary Asic Rtl Design Engineer vs Temporary FPGA Design Engineer?

AspectTemporary Asic Rtl Design EngineerTemporary FPGA Design Engineer
Primary FocusDesigning RTL code for ASIC chipsDesigning FPGA logic and configurations
Skills & CertificationsVerilog/VHDL, ASIC design flow, simulation toolsVerilog/VHDL, FPGA development tools, synthesis
Work EnvironmentSemiconductor companies, ASIC design teamsFPGA development labs, prototyping environments
Industry UsageUsed in high-volume chip manufacturingUsed for prototyping, testing, and low-volume products

Both roles involve RTL design using Verilog or VHDL, but the Temporary Asic Rtl Design Engineer focuses on ASIC chip development, while the Temporary FPGA Design Engineer specializes in FPGA-based prototyping and testing. The choice depends on whether the project aims for mass production or flexible, rapid development.

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16218 - ASIC Digital Design, Sr Manager

16218 - ASIC Digital Design, Sr Manager

Synopsys

Sunnyvale, CA • On-site

$204K/yr

Full-time

Posted 18 days ago


Job description

General Information
Job Title
ASIC Digital Design, Sr Manager
Job ID
16218
City
Sunnyvale
State/Province
California
Date Posted
12-Mar-2026
Job Category
Engineering
Job Subcategory
ASIC Digital Design
Hire Type
Employee
Remote Eligible
No
Base Salary Range: $204000 - $306000
Descriptions & Requirements
Job Description and Requirements
You Are:
You are an experienced ASIC Digital Design Manager with strong hands-on expertise in USB digital design and architecture, capable of leading a team while remaining deeply engaged in technical execution. You bring extensive experience defining and implementing RTL and micro-architecture for complex, high-speed interface IP, combined with proven team-lead and people-management skills.
You setting technical direction with your team, making architectural trade-offs, and driving design decisions . You are comfortable working directly with RTL, reviewing detailed design implementations, and guiding engineers through complex debug and convergence challenges. Your background includes exposure to USB or similar protocols.
As a experienced leader, you foster a culture of accountability, collaboration, and technical excellence. You mentor engineers through hands-on guidance and design reviews, communicate clearly across disciplines, and work closely with cross-functional teams to deliver high-quality, silicon-proven USB IP .
What You'll Be Doing:
Leading and managing a team of ASIC digital design engineers, providing day-to-day technical guidance, mentoring, and performance management.
• Owning USB digital architecture and RTL design execution, remaining hands-on while leading design efforts at block, subsystem, and IP-integration levels.
• Defining micro-architecture, design specifications, and implementation approaches for high-performance, power-efficient, and scalable PCIe designs.
• Leading end-to-end digital design activities, including architecture definition, RTL development, debug, design convergence, and post-silicon support.
• Planning and prioritizing design work, balancing hands-on technical involvement with team execution, schedules, and resource needs.
• Driving design quality through rigorous design reviews, coding standards, and RTL maintainability practices.
• Collaborating closely with verification, validation teams to ensure smooth IP integration and silicon success.
• Coaching and developing engineers through hands-on technical mentoring, design feedback, and career development discussions.
• Promoting a culture of technical ownership, accountability, and continuous improvement within the team.
• Identifying opportunities to improve AI- driven design methodologies, workflows, and productivity, while keeping focus on design execution.
• Communicating design status, technical risks, and trade-offs effectively to senior management and cross-functional stakeholders.
The Impact You Will Have:
• Deliver industry-leading USB digital IP with high performance, robustness, and scalability.
• Drive strong architectural and design execution for USB IP used by leading customers.
• Improve design quality, predictability, and execution efficiency through strong technical leadership.
• Build and lead a highly capable ASIC digital design team with deep USB expertise.
• Strengthen Synopsys' position as a leader in high-speed interface IP across commercial, enterprise, and automotive markets.
What You'll Need:
• Bachelor's degree in Electrical Engineering (BSEE) with 12+ years of experience, or Master's degree (MSEE) with 10+ years.
• Demonstrated experience as a team lead or people manager in an ASIC digital design environment.
• Extensive hands-on ASIC RTL design experience, with direct ownership of complex digital designs.
• Deep expertise in USB digital design and architecture or similar protocols.
• Strong understanding of ASIC design fundamentals including clocking, resets, low-power techniques, and design for test.
• Experience with AI-driven tools, flows and methodologies. Familiarity with scripting languages (Perl, TCL, Python) for design automation is a plus.
At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.
In addition to the base salary, this role may be eligible for an annual bonus, equity, and other discretionary bonuses. Synopsys offers comprehensive health, wellness, and financial benefits as part of a competitive total rewards package. The actual compensation offered will be based on a number of job-related factors, including location, skills, experience, and education. Your recruiter can share more specific details on the total rewards package upon request. The base salary range for this role is across the U.S.

Synopsys logo

About Synopsys

Sourced by ZipRecruiter

Synopsys, Inc. (Nasdaq:SNPS) is the Silicon to Software partner for creative companies developing the electronic products and software applications we rely on every single day. As the world's 15th largest software company, Synopsys has a long history of being a global leader in electronic design automation (EDA) and semiconductor IP and is also growing its leadership in software quality and security solutions. Whether you're a system-on-chip (SoC) designer building advanced semiconductors, or a software developer writing applications that require the highest quality and security, Synopsys has the solutions needed to deliver exceptional, secure products for the era of connected everything. The company is headquartered in Mountain View, California, and has approximately 113 offices located throughout North America, South America, Europe, Japan, Asia and India. Since 1986, Synopsys has been at the heart of accelerating electronics innovation with engineers around the world having used Synopsys technology to successfully design and create billions of chips and systems that are found in the electronics that people rely on every single day.

Industry

Computer and computer peripheral equipment and software wholesalers

Company size

10,000+ Employees

Headquarters location

Mountain View, CA, US

Year founded

1986

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