RTL Engineer - Networking ASIC Saratoga, CA Full-Time Join an innovative hardware company building ... Design packet buffering, queuing, and scheduling microarchitecture * Implement high-speed ...
RTL Engineer - Networking ASIC Saratoga, CA Full-Time Join an innovative hardware company building ... Design packet buffering, queuing, and scheduling microarchitecture * Implement high-speed ...
Processor ASIC RTL Design Engineer
San Diego, CA ยท On-site
$127K - $190K/yr
Engineering Group, Engineering Group > DSP Architecture and Design General Summary: A variety of ... This position involves in-depth understanding of the ASIC design flow from RTL to GDS2 and the ...
Processor ASIC RTL Design Engineer
San Diego, CA ยท On-site
$127K - $190K/yr
Engineering Group, Engineering Group > DSP Architecture and Design General Summary: A variety of ... This position involves in-depth understanding of the ASIC design flow from RTL to GDS2 and the ...
We're seeking engineers who are energized by working on cutting-edge ASIC design and distributed ... Own ASIC RTL delivery schedules across major milestones by tracking, monitoring, and reporting ...
We're seeking engineers who are energized by working on cutting-edge ASIC design and distributed ... Own ASIC RTL delivery schedules across major milestones by tracking, monitoring, and reporting ...
ASIC/ SoC RTL Design Engineer
Burlingame, CA ยท On-site
ASIC/SoC RTL Design Engineer Location: Palo Alto, CA (Or potentially Burlington, MA) Length of Contract: 6 months+ (Temp-to-Perm) Ideal Start: 6/1/2026 Responsibilities : Own end-to-end design of ...
ASIC/ SoC RTL Design Engineer
Burlingame, CA ยท On-site
ASIC/SoC RTL Design Engineer Location: Palo Alto, CA (Or potentially Burlington, MA) Length of Contract: 6 months+ (Temp-to-Perm) Ideal Start: 6/1/2026 Responsibilities : Own end-to-end design of ...
ASIC/RTL Design Engineer 2
San Jose, CA ยท On-site
$60 - $62/hr
Hands-on experience in industry ASIC design flow including RTL coding, debugging/verification, and supporting synthesis and timing closure. * Working knowledge of Client cores and other I/O standard ...
Quick apply
ASIC/RTL Design Engineer 2
San Jose, CA ยท On-site
$60 - $62/hr
Hands-on experience in industry ASIC design flow including RTL coding, debugging/verification, and supporting synthesis and timing closure. * Working knowledge of Client cores and other I/O standard ...
Senior ASIC (Front-End) Design Engineer
San Jose, CA ยท Hybrid
$200K - $300K/yr
As a Senior ASIC Front-End Design Engineer, you will be responsible for all aspects of digital SoC design , from micro-architecture specification, RTL, verification, synthesis, lint, CDC, LEC, and ...
Senior ASIC (Front-End) Design Engineer
San Jose, CA ยท Hybrid
$200K - $300K/yr
As a Senior ASIC Front-End Design Engineer, you will be responsible for all aspects of digital SoC design , from micro-architecture specification, RTL, verification, synthesis, lint, CDC, LEC, and ...
Physical Design Engineer - Synthesis & Floorplanning
Sunnyvale, CA ยท On-site
$161K - $166K/yr
Prodapt's ASIC Services is a leading provider of SoC/ASIC RTL Design, UVM based verification ... We are hiring an experienced Physical Design Engineer to join a high-performing silicon engineering ...
Physical Design Engineer - Synthesis & Floorplanning
Sunnyvale, CA ยท On-site
$161K - $166K/yr
Prodapt's ASIC Services is a leading provider of SoC/ASIC RTL Design, UVM based verification ... We are hiring an experienced Physical Design Engineer to join a high-performing silicon engineering ...
ASIC/RTL Design Engineer Primary Skills : RTL coding, TCL coding, Python coding, understanding of different CAD tools (synthesis, lint, CDC, RDC, PrimeTime). Location: San Jose CA Duration : 12 ...
ASIC/RTL Design Engineer Primary Skills : RTL coding, TCL coding, Python coding, understanding of different CAD tools (synthesis, lint, CDC, RDC, PrimeTime). Location: San Jose CA Duration : 12 ...
ASIC RTL/SoC Design Engineer
Fremont, CA ยท On-site
Lead RTL design, simulation, and verification efforts for TetraMem ASIC/SoC products, ensuring ... Play a mentorship role by guiding and coaching junior engineers, sharing expertise and best ...
ASIC RTL/SoC Design Engineer
Fremont, CA ยท On-site
Lead RTL design, simulation, and verification efforts for TetraMem ASIC/SoC products, ensuring ... Play a mentorship role by guiding and coaching junior engineers, sharing expertise and best ...
As a Senior ASIC Design Engineer, you will own the complete RTL design lifecycle from micro-architecture specification through production silicon, working on complex IP design. THE PERSON: The ideal ...
As a Senior ASIC Design Engineer, you will own the complete RTL design lifecycle from micro-architecture specification through production silicon, working on complex IP design. THE PERSON: The ideal ...
ASIC RTL/SoC Design Engineer
Fremont, CA ยท On-site
Lead RTL design, simulation, and verification efforts for TetraMem ASIC/SoC products, ensuring ... Play a mentorship role by guiding and coaching junior engineers, sharing expertise and best ...
ASIC RTL/SoC Design Engineer
Fremont, CA ยท On-site
Lead RTL design, simulation, and verification efforts for TetraMem ASIC/SoC products, ensuring ... Play a mentorship role by guiding and coaching junior engineers, sharing expertise and best ...
Integration RTL Design Engineer
San Jose, CA ยท On-site
$145K/yr
As a Senior ASIC Design Engineer, you will own the complete RTL design lifecycle from micro-architecture specification through production silicon, working on complex IP design. THE PERSON: The ideal ...
Integration RTL Design Engineer
San Jose, CA ยท On-site
$145K/yr
As a Senior ASIC Design Engineer, you will own the complete RTL design lifecycle from micro-architecture specification through production silicon, working on complex IP design. THE PERSON: The ideal ...
ASIC/SoC Design Engineer, RTL design for SoC IPs
San Jose, CA ยท On-site
$145K/yr
As a Senior ASIC Design Engineer, you will own the complete RTL design lifecycle from micro-architecture specification through production silicon, working on complex IP design. THE PERSON: The ideal ...
ASIC/SoC Design Engineer, RTL design for SoC IPs
San Jose, CA ยท On-site
$145K/yr
As a Senior ASIC Design Engineer, you will own the complete RTL design lifecycle from micro-architecture specification through production silicon, working on complex IP design. THE PERSON: The ideal ...
As a Senior ASIC Design Engineer, you will own the complete RTL design lifecycle from micro-architecture specification through production silicon, working on complex IP design. THE PERSON: The ideal ...
As a Senior ASIC Design Engineer, you will own the complete RTL design lifecycle from micro-architecture specification through production silicon, working on complex IP design. THE PERSON: The ideal ...
ASIC RTL/SoC Design Engineer
$110K - $300K/yr
Lead RTL design, simulation, and verification efforts for TetraMem ASIC/SoC products, ensuring ... Play a mentorship role by guiding and coaching junior engineers, sharing expertise and best ...
ASIC RTL/SoC Design Engineer
$110K - $300K/yr
Lead RTL design, simulation, and verification efforts for TetraMem ASIC/SoC products, ensuring ... Play a mentorship role by guiding and coaching junior engineers, sharing expertise and best ...
... RTL designs - Working with design verification and formal verification teams to verify ... front-end ASIC RTL design Tight-knit collaboration skills with excellent written and verbal ...
... RTL designs - Working with design verification and formal verification teams to verify ... front-end ASIC RTL design Tight-knit collaboration skills with excellent written and verbal ...
... RTL designs - Working with design verification and formal verification teams to verify ... front-end ASIC RTL design Tight-knit collaboration skills with excellent written and verbal ...
... RTL designs - Working with design verification and formal verification teams to verify ... front-end ASIC RTL design Tight-knit collaboration skills with excellent written and verbal ...
... RTL designs - Working with design verification and formal verification teams to verify ... front-end ASIC RTL design Tight-knit collaboration skills with excellent written and verbal ...
... RTL designs - Working with design verification and formal verification teams to verify ... front-end ASIC RTL design Tight-knit collaboration skills with excellent written and verbal ...
Staff RTL Engineer - Ethernet Saratoga, CA Full-Time Join a cutting-edge hardware company building ... MSEE with 8-15 years of ASIC/RTL design experience * Strong expertise in Ethernet 802.3 protocols ...
Staff RTL Engineer - Ethernet Saratoga, CA Full-Time Join a cutting-edge hardware company building ... MSEE with 8-15 years of ASIC/RTL design experience * Strong expertise in Ethernet 802.3 protocols ...
RTL Design Engineer Building AI chips that are hard-coded for individual model architectures. RTL ... both our existing and upcoming ASIC designs. In this role, you will work closely with ...
Quick apply
RTL Design Engineer Building AI chips that are hard-coded for individual model architectures. RTL ... both our existing and upcoming ASIC designs. In this role, you will work closely with ...
Telecommute Asic Rtl Design Engineer information
What are some common challenges faced by telecommute ASIC RTL Design Engineers, and how can they be addressed?
What are the key skills and qualifications needed to thrive as a Telecommute ASIC RTL Design Engineer, and why are they important?
What is a Telecommute ASIC RTL Design Engineer?
What is the difference between Telecommute Asic Rtl Design Engineer vs Telecommute Digital IC Design Engineer?
| Aspect | Telecommute Asic Rtl Design Engineer | Telecommute Digital IC Design Engineer |
|---|---|---|
| Credentials | Bachelor's or Master's in Electrical Engineering or Computer Engineering; experience with RTL coding | Bachelor's or Master's in Electrical Engineering or Computer Engineering; experience with digital circuit design |
| Work Environment | Remote, primarily designing RTL code for ASICs | Remote, focusing on digital IC architecture and design |
| Industry Usage | Common in semiconductor and electronics companies |
Both roles often require similar educational backgrounds and work remotely in the semiconductor industry. The main difference lies in their focus: RTL Design Engineers concentrate on writing RTL code for ASICs, while Digital IC Design Engineers work on broader digital circuit architecture. Candidates should choose based on their specific skills and career interests in digital design or RTL coding.
Other
Posted 15 days ago
Job description
Saratoga, CA
Full-Time
Join an innovative hardware company building next-generation Networking ASICs that power large-scale AI training and inference.
We are seeking experienced RTL Engineers to architect and implement high-performance networking chips focused on low latency, QoS, and scalability.
Responsibilities-
Design packet buffering, queuing, and scheduling microarchitecture
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Implement high-speed networking ASIC RTL (SystemVerilog/Verilog)
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Optimize pipelined architectures for performance and latency
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Support Ethernet, IP protocols, and high-speed interconnects (e.g., UCIe)
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Collaborate with verification teams for testing and validation
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BE/ME with 8โ15 years of ASIC RTL design experience
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Strong expertise in SystemVerilog & Verilog
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Experience with scheduling, arbitration & QoS mechanisms
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Solid understanding of ASIC design flow (simulation, synthesis, timing)
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Background in Ethernet and IP networking protocols
If youโre passionate about building high-speed networking silicon for AI infrastructure, apply today.