ZipRecruiter

Log In

1

Telecommute Asic Rtl Design Engineer Jobs in California

Qualcomm

Processor ASIC RTL Design Engineer

San Diego, CA · On-site

$127.20K - $190.80K/yr

Engineering Group, Engineering Group > DSP Architecture and Design General Summary: A variety of ... This position involves in-depth understanding of the ASIC design flow from RTL to GDS2 and the ...

TetraMem Inc

ASIC RTL/SoC Design Engineer

San Jose, CA · On-site

$110K - $300K/yr

Lead RTL design, simulation, and verification efforts for TetraMem ASIC/SoC products, ensuring ... Play a mentorship role by guiding and coaching junior engineers, sharing expertise and best ...

TetraMem INC

ASIC RTL/SoC Design Engineer

Fremont, CA · On-site

Lead RTL design, simulation, and verification efforts for TetraMem ASIC/SoC products, ensuring ... Play a mentorship role by guiding and coaching junior engineers, sharing expertise and best ...

TetraMem INC

ASIC RTL/SoC Design Engineer

Fremont, CA · On-site

Lead RTL design, simulation, and verification efforts for TetraMem ASIC/SoC products, ensuring ... Play a mentorship role by guiding and coaching junior engineers, sharing expertise and best ...

next page

Showing results 1-20

People also search for

All JobsTelecommute Asic Rtl Design Engineer JobsTelecommute Asic Rtl Design Engineer Jobs in California

Telecommute Asic Rtl Design Engineer information

What are the key skills and qualifications needed to thrive as a Telecommute ASIC RTL Design Engineer, and why are they important?

To thrive as a Telecommute ASIC RTL Design Engineer, you need a strong background in digital logic design, proficiency in hardware description languages like Verilog or VHDL, and typically a degree in electrical or computer engineering. Familiarity with EDA tools such as Synopsys or Cadence, as well as experience with simulation, synthesis, and debugging environments, is essential. Strong problem-solving abilities, attention to detail, and effective communication skills are crucial for collaborating remotely and ensuring design accuracy. These skills are vital to deliver complex, high-performance ASICs on schedule while working efficiently in a remote setting.

What are some common challenges faced by telecommute ASIC RTL Design Engineers, and how can they be addressed?

Telecommute ASIC RTL Design Engineers often face challenges like coordinating effectively with remote teams, ensuring version control integrity, and maintaining clear communication on project specifications. These challenges can be mitigated by utilizing robust collaboration tools, adhering to standardized documentation practices, and scheduling regular virtual meetings for design reviews. Additionally, staying proactive in seeking feedback and clarifying requirements helps ensure alignment and prevents costly design iterations.

What is a Telecommute ASIC RTL Design Engineer?

A Telecommute ASIC RTL Design Engineer is a professional who specializes in designing digital circuits at the Register Transfer Level (RTL) for Application-Specific Integrated Circuits (ASICs), while working remotely. They use hardware description languages like Verilog or VHDL to create and verify circuit designs tailored to specific applications. Their responsibilities often include developing, simulating, and optimizing digital logic, collaborating with cross-functional teams, and ensuring that the final silicon meets design specifications. Since the role is telecommute, all work is performed from a remote location using digital communication and collaboration tools.

What is the difference between Telecommute Asic Rtl Design Engineer vs Telecommute Digital IC Design Engineer?

AspectTelecommute Asic Rtl Design EngineerTelecommute Digital IC Design Engineer
CredentialsBachelor's or Master's in Electrical Engineering or Computer Engineering; experience with RTL codingBachelor's or Master's in Electrical Engineering or Computer Engineering; experience with digital circuit design
Work EnvironmentRemote, primarily designing RTL code for ASICsRemote, focusing on digital IC architecture and design
Industry UsageCommon in semiconductor and electronics companies

Both roles often require similar educational backgrounds and work remotely in the semiconductor industry. The main difference lies in their focus: RTL Design Engineers concentrate on writing RTL code for ASICs, while Digital IC Design Engineers work on broader digital circuit architecture. Candidates should choose based on their specific skills and career interests in digital design or RTL coding.

What are the most commonly searched types of Asic Rtl Design Engineer jobs in California? The most popular types of Asic Rtl Design Engineer jobs in California are:
What are popular job titles related to Telecommute Asic Rtl Design Engineer jobs in California? For Telecommute Asic Rtl Design Engineer jobs in California, the most frequently searched job titles are:
What job categories do people searching Telecommute Asic Rtl Design Engineer jobs in California look for? The top searched job categories for Telecommute Asic Rtl Design Engineer jobs in California are:
What cities in California are hiring for Telecommute Asic Rtl Design Engineer jobs? Cities in California with the most Telecommute Asic Rtl Design Engineer job openings:
Telecommute Asic Rtl Design Engineer jobs near you

Lead ASIC RTL Design Engineer

4 Staffing Corp - Client Jobs

San Francisco, CA • On-site, Remote

$170K - $250K/yr

Full-time

Posted 15 days ago

Job description

Lead ASIC RTL Design Engineer — Remote (U.S.) - No visa sponsorship

Role Summary
Our client, a leader in AI Compute is seeking a senior-level ASIC design engineer to drive the development of high-performance silicon components used in advanced compute platforms. This individual will take ownership of key IP blocks from early architectural definition through RTL delivery and signoff, working closely with cross-functional teams to meet aggressive performance, power, and area goals. The role combines hands-on design work with technical leadership and mentorship.

Core Responsibilities

Architecture & RTL Development

  • Define microarchitecture for complex subsystems and document design specifications
  • Implement high-quality, reusable RTL in System Verilog with clear interface definitions and design intent
  • Incorporate assertions and design-for-debug features within RTL

Design Ownership & Implementation

  • Lead front-end design activities including linting, clock/reset domain analysis, and synthesis readiness
  • Collaborate with physical design teams on floor planning, timing closure, and implementation tradeoffs
  • Take responsibility for achieving performance, power, and area (PPA) targets for assigned blocks

High-Speed Interfaces & Memory Systems

  • Design and integrate high-bandwidth interfaces and interconnects (e.g., AMBA-based protocols, coherent fabrics)
  • Work on memory subsystem integration, including external DRAM and high-throughput memory solutions
  • Coordinate with internal teams and third-party IP providers to ensure proper integration and functionality

Engineering Processes & Tooling

  • Establish and maintain RTL design standards, reusable components, and signoff criteria
  • Contribute to automation and workflow improvements using scripting and build systems (Python, Tcl, CI pipelines)

Collaboration & System Integration

  • Partner with verification teams on test planning, coverage goals, and model alignment
  • Work with architecture and performance engineering to validate design intent against system-level expectations
  • Support silicon bring-up, debugging, and downstream customer or system integration efforts

Technical Leadership

  • Mentor less experienced engineers and provide guidance on design best practices
  • Lead design reviews and help drive key technical decisions across teams
  • Advocate for scalable, efficient, and high-quality engineering solutions

Basic Qualifications

  • Bachelor's or Master's degree in Electrical or Computer Engineering (or similar field)
  • 8+ years of experience in ASIC or SoC RTL design for complex, high-speed devices
  • Demonstrated experience delivering designs from concept through RTL implementation and tape out readiness
  • Strong System Verilog expertise, including clocking strategies, reset design, and domain crossing considerations
  • Hands-on experience with front-end design tools and flows (linting, CDC analysis, synthesis, timing analysis, DFT)
  • Familiarity with multiple high-speed technologies such as memory interfaces, interconnect protocols, or compute data paths
  • Strong communication skills with the ability to lead technical discussions and document designs clearly

Preferred Experience

  • Exposure to AI/ML hardware or high-performance compute architectures
  • Knowledge of formal verification techniques and assertion-based design
  • Experience with power optimization methods (e.g., clock gating, power intent formats like UPF/CPF)
  • Familiarity working alongside verification environments (UVM, Python-based frameworks, or similar)
  • Understanding of modern processor subsystems, coherence models, or custom tool flows