ASIC Design Engineer Responsibilities: * Define and bring up FPGA platforms for pre-silicon ... Map ASIC RTL to FGPA while minimizing code base differences * Create and execute test plans for ...
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ASIC Design Engineer Responsibilities: * Define and bring up FPGA platforms for pre-silicon ... Map ASIC RTL to FGPA while minimizing code base differences * Create and execute test plans for ...
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New
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New
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ASIC Design Engineer lll This role has been designed as ''Onsite' with an expectation that you will ... Perform RTL linting, CDC analysis, synthesis, and timing closure support. * Develop design ...
ASIC Design Engineer lll This role has been designed as ''Onsite' with an expectation that you will ... Perform RTL linting, CDC analysis, synthesis, and timing closure support. * Develop design ...
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ASIC Design Engineer lll This role has been designed as ''Onsite' with an expectation that you will ... Perform RTL linting, CDC analysis, synthesis, and timing closure support. * Develop design ...
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Sunnyvale, CA · On-site
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San Jose, CA · On-site
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RTL Design Engineer
San Jose, CA · On-site
$150K - $275K/yr
Job Summary As an RTL Engineer at Etched, you will be critical in ensuring that our AI chips ... both our existing and upcoming ASIC designs. In this role, you will work closely with ...
Quick apply
RTL Design Engineer
San Jose, CA · On-site
$150K - $275K/yr
Job Summary As an RTL Engineer at Etched, you will be critical in ensuring that our AI chips ... both our existing and upcoming ASIC designs. In this role, you will work closely with ...
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We are looking for talented engineers and leaders who have an entrepreneurial spirit and want to ... Minimum 10+ years of ASIC RTL design and/or architecture experience * Proven track record with the ...
Power Engineer (RTL Design)
Sunnyvale, CA · On-site
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Power Engineer (RTL Design)
Sunnyvale, CA · On-site
ASIC/SOC power engineers with experience on tools like PTPX / RTL-A. • We are seeking a highly skilled and motivated Contract Worker for RTL Design and Verification with expertise in power ...
THE OPPORTUNITY Silvus is seeking a Principal FPGA / RTL Design Engineer- Signal Processing who ... Experience with wireless communication systems on FPGA or ASIC designs. WORKING CONDITIONS ...
THE OPPORTUNITY Silvus is seeking a Principal FPGA / RTL Design Engineer- Signal Processing who ... Experience with wireless communication systems on FPGA or ASIC designs. WORKING CONDITIONS ...
Temporary Asic Rtl Design Engineer information
What is the difference between Temporary Asic Rtl Design Engineer vs Temporary FPGA Design Engineer?
| Aspect | Temporary Asic Rtl Design Engineer | Temporary FPGA Design Engineer |
|---|---|---|
| Primary Focus | Designing RTL code for ASIC chips | Designing FPGA logic and configurations |
| Skills & Certifications | Verilog/VHDL, ASIC design flow, simulation tools | Verilog/VHDL, FPGA development tools, synthesis |
| Work Environment | Semiconductor companies, ASIC design teams | FPGA development labs, prototyping environments |
| Industry Usage | Used in high-volume chip manufacturing | Used for prototyping, testing, and low-volume products |
Both roles involve RTL design using Verilog or VHDL, but the Temporary Asic Rtl Design Engineer focuses on ASIC chip development, while the Temporary FPGA Design Engineer specializes in FPGA-based prototyping and testing. The choice depends on whether the project aims for mass production or flexible, rapid development.
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Full-time
Re-posted 15 days ago
Job description
ASIC Design Engineer
Responsibilities:
- Define and bring up FPGA platforms for pre-silicon validation and software development
- Map ASIC RTL to FGPA while minimizing code base differences
- Create and execute test plans for validating SoC functionality and performance
- Resolve challenging system level issues that span multiple disciplines
- Design logic starting from specification or high level feature description
Requirements:
- Minimum of 5 years of relevant experience.
- Scripting or programming experience in Python or C/C++
- Ability to write and analyze the completeness of constraints
- Familiarity with lab equipment including logic analyzers, oscilloscopes, and multimeters
- Strong analytical and debugging skills
- BS in Electrical Engineering or equivalent required, MS preferred
Nice to Have:
- Familiarity with Xilinx FPGA’s and Vivado tool chain
- Experience with validating and debugging low-power wireless systems
- Understanding of common interfaces and bus protocols (e.g. I2C, SPI, AHB)
- Knowledge of wireless protocols (e.g. Bluetooth Low Energy)
About Ethan Alexander Group
Sourced by ZipRecruiter
Industry
Recruiting and staffing services
Company size
1 - 10 Employees
Headquarters location
Mission Hills, CA, US
Year founded
2013