Sunnyvale, CA · On-site +1
$204K - $306K/yr
... RTL, reviewing detailed design implementations, and guiding engineers through complex debug and ... Leading and managing a team of ASIC digital design engineers, providing daytoday technical guidance ...
Sunnyvale, CA · On-site +1
$204K - $306K/yr
... RTL, reviewing detailed design implementations, and guiding engineers through complex debug and ... Leading and managing a team of ASIC digital design engineers, providing daytoday technical guidance ...
RTL Design Engineer As an RTL Engineer at Etched, you will be critical in ensuring that our AI ... both our existing and upcoming ASIC designs. In this role, you will work closely with ...
RTL Design Engineer As an RTL Engineer at Etched, you will be critical in ensuring that our AI ... both our existing and upcoming ASIC designs. In this role, you will work closely with ...
ASIC / VLSI ENGINEERS - RTL / STA / PD / DV (Senior Level) We are hiring 4 experienced ASIC / VLSI ... RTL Engineer (Networking / Ethernet) * STA Engineer * Physical Design Engineer * Design ...
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ASIC / VLSI ENGINEERS - RTL / STA / PD / DV (Senior Level) We are hiring 4 experienced ASIC / VLSI ... RTL Engineer (Networking / Ethernet) * STA Engineer * Physical Design Engineer * Design ...
Cupertino, CA · On-site
$2K/mo
RTL Design Engineer As an RTL Engineer at Etched, you will be critical in ensuring that our AI ... both our existing and upcoming ASIC designs. In this role, you will work closely with ...
Cupertino, CA · On-site
$2K/mo
RTL Design Engineer As an RTL Engineer at Etched, you will be critical in ensuring that our AI ... both our existing and upcoming ASIC designs. In this role, you will work closely with ...
Sunnyvale, CA · On-site
$159.60K/yr
Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience. * 2 years of experience in ASIC RTL design, with a focus on ...
Sunnyvale, CA · On-site
$159.60K/yr
Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience. * 2 years of experience in ASIC RTL design, with a focus on ...
Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience. * 4 years of experience in ASIC RTL design, with a focus on ...
Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience. * 4 years of experience in ASIC RTL design, with a focus on ...
$140K - $175K/yr
RTL DESIGN ENGINEER (SILICON ENGINEERING) At SpaceX we're leveraging our experience in building ... Participate in the full ASIC/FPGA design lifecycle for Starlink projects, from high-level ...
$140K - $175K/yr
RTL DESIGN ENGINEER (SILICON ENGINEERING) At SpaceX we're leveraging our experience in building ... Participate in the full ASIC/FPGA design lifecycle for Starlink projects, from high-level ...
Knowledge of ASIC flow, SerDes, and scripting. About the job In this role, you'll work to shape the ... As a PCIe Design Engineer, you will architect and implement SoC-level RTL for our next-generation ...
Knowledge of ASIC flow, SerDes, and scripting. About the job In this role, you'll work to shape the ... As a PCIe Design Engineer, you will architect and implement SoC-level RTL for our next-generation ...
Sunnyvale, CA · On-site
$204K - $306K/yr
General Information Job Title ASIC Digital Design, Sr Manager Job ID 16218 City Sunnyvale State ... RTL, reviewing detailed design implementations, and guiding engineers through complex debug and ...
Sunnyvale, CA · On-site
$204K - $306K/yr
General Information Job Title ASIC Digital Design, Sr Manager Job ID 16218 City Sunnyvale State ... RTL, reviewing detailed design implementations, and guiding engineers through complex debug and ...
Sunnyvale, CA · Hybrid
$175K - $275K/yr
About The Role As a lead front-end design engineer, you will be a key part of the world-class team ... The role also requires close collaboration and management of external ASIC vendor. You will ...
Sunnyvale, CA · Hybrid
$175K - $275K/yr
About The Role As a lead front-end design engineer, you will be a key part of the world-class team ... The role also requires close collaboration and management of external ASIC vendor. You will ...
Sunnyvale, CA · On-site
ASIC/SOC power engineers with experience on tools like PTPX / RTL-A. • We are seeking a highly skilled and motivated Contract Worker for RTL Design and Verification with expertise in power ...
New
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Sunnyvale, CA · On-site
ASIC/SOC power engineers with experience on tools like PTPX / RTL-A. • We are seeking a highly skilled and motivated Contract Worker for RTL Design and Verification with expertise in power ...
New
The role spans from RTL design through timing closure and tapeout readiness, with increasing ... engineers. Ideal candidates have 3+ years of industrial ASIC experience and a proven track record ...
The role spans from RTL design through timing closure and tapeout readiness, with increasing ... engineers. Ideal candidates have 3+ years of industrial ASIC experience and a proven track record ...
$132K - $181.90K/yr
THE OPPORTUNITY Silvus is seeking a Principal FPGA / RTL Design Engineer- Signal Processing who ... Experience with wireless communication systems on FPGA or ASIC designs. WORKING CONDITIONS ...
$132K - $181.90K/yr
THE OPPORTUNITY Silvus is seeking a Principal FPGA / RTL Design Engineer- Signal Processing who ... Experience with wireless communication systems on FPGA or ASIC designs. WORKING CONDITIONS ...
We are seeking a Senior ASIC Design Engineer with seasoned experience in the development of high ... The ideal candidate has hands-on experience across the full ASIC development cycle -- from RTL ...
We are seeking a Senior ASIC Design Engineer with seasoned experience in the development of high ... The ideal candidate has hands-on experience across the full ASIC development cycle -- from RTL ...
$194.60K/yr
ASIC Engineer Location: San Jose, CA Duration: 6 Months Minimum Required Skills ... ASIC Design, FPGA, RTL Design, Chip Architecture, ASIC, Implementation,Synthesis /Conformal ...
$194.60K/yr
ASIC Engineer Location: San Jose, CA Duration: 6 Months Minimum Required Skills ... ASIC Design, FPGA, RTL Design, Chip Architecture, ASIC, Implementation,Synthesis /Conformal ...
We are looking for talented engineers and leaders who have an entrepreneurial spirit and want to ... Minimum 10+ years of ASIC RTL design and/or architecture experience * Proven track record with the ...
We are looking for talented engineers and leaders who have an entrepreneurial spirit and want to ... Minimum 10+ years of ASIC RTL design and/or architecture experience * Proven track record with the ...
$126.80K - $190.90K/yr
... RTL designs - Working with design verification and formal verification teams to verify ... front-end ASIC RTL design Tight-knit collaboration skills with excellent written and verbal ...
$126.80K - $190.90K/yr
... RTL designs - Working with design verification and formal verification teams to verify ... front-end ASIC RTL design Tight-knit collaboration skills with excellent written and verbal ...
ASIC/SOC power engineers with experience on tools like PTPX / RTL-A. • We are seeking a highly skilled and motivated Contract Worker for RTL Design and Verification with expertise in power ...
ASIC/SOC power engineers with experience on tools like PTPX / RTL-A. • We are seeking a highly skilled and motivated Contract Worker for RTL Design and Verification with expertise in power ...
$147.40K - $272.10K/yr
... RTL designs - Working with design verification and formal verification teams to verify ... front-end ASIC RTL design Tight-knit collaboration skills with excellent written and verbal ...
$147.40K - $272.10K/yr
... RTL designs - Working with design verification and formal verification teams to verify ... front-end ASIC RTL design Tight-knit collaboration skills with excellent written and verbal ...
$120K - $225K/yr
We're hiring experienced RTL Design Engineers from junior to senior levels to play a key role in designing and implementing the components that will bring our next-generation AI processors to life.
$120K - $225K/yr
We're hiring experienced RTL Design Engineers from junior to senior levels to play a key role in designing and implementing the components that will bring our next-generation AI processors to life.
| Aspect | Temporary Asic Rtl Design Engineer | Temporary FPGA Design Engineer |
|---|---|---|
| Primary Focus | Designing RTL code for ASIC chips | Designing FPGA logic and configurations |
| Skills & Certifications | Verilog/VHDL, ASIC design flow, simulation tools | Verilog/VHDL, FPGA development tools, synthesis |
| Work Environment | Semiconductor companies, ASIC design teams | FPGA development labs, prototyping environments |
| Industry Usage | Used in high-volume chip manufacturing | Used for prototyping, testing, and low-volume products |
Both roles involve RTL design using Verilog or VHDL, but the Temporary Asic Rtl Design Engineer focuses on ASIC chip development, while the Temporary FPGA Design Engineer specializes in FPGA-based prototyping and testing. The choice depends on whether the project aims for mass production or flexible, rapid development.
$204K - $306K/yr
Other
Posted 16 days ago
You Are:
You are an experiencedASIC Digital Design Managerwithstrong handson expertise in USB digital design and architecture, capable ofleading a team while remaining deeply engaged in technical execution. You bring extensive experience defining and implementingRTL and microarchitecture for complex, highspeed interface IP, combined with proven teamlead and peoplemanagement skills.
You setting technical direction with your team, making architectural tradeoffs, and driving design decisions . You are comfortable working directly with RTL, reviewing detailed design implementations, and guiding engineers through complex debug and convergence challenges. Your background includes exposure to USB or similar protocols.
As a experienced leader, you foster a culture of accountability, collaboration, and technical excellence. You mentor engineers through handson guidance and design reviews, communicate clearly across disciplines, and work closely with crossfunctional teams to deliverhighquality, siliconproven USB IP.
What You'll Be Doing:
Leading and managing a team of ASIC digital design engineers, providing daytoday technical guidance, mentoring, and performance management.
* OwningUSB digital architecture and RTL design execution, remaining handson while leading design efforts at block, subsystem, and IPintegration levels.
* Defining microarchitecture, design specifications, and implementation approaches for highperformance, powerefficient, and scalable PCIe designs.
* Leading endtoend digital design activities, including architecture definition, RTL development, debug, design convergence, and postsilicon support.
* Planning and prioritizing design work, balancing handson technical involvement with team execution, schedules, and resource needs.
* Driving design quality through rigorous design reviews, coding standards, and RTL maintainability practices.
* Collaborating closely with verification, validation teams to ensure smooth IP integration and silicon success.
* Coaching and developing engineers through handson technical mentoring, design feedback, and career development discussions.
* Promoting a culture of technical ownership, accountability, and continuous improvement within the team.
* Identifying opportunities to improve AI- driven design methodologies, workflows, and productivity, while keeping focus on design execution.
* Communicating design status, technical risks, and tradeoffs effectively to senior management and crossfunctional stakeholders.
The Impact You Will Have:
* Deliverindustryleading USB digital IPwith high performance, robustness, and scalability.
* Drive strong architectural and design execution for USB IP used by leading customers.
* Improve design quality, predictability, and execution efficiency through strong technical leadership.
* Build and lead a highly capable ASIC digital design team with deep USB expertise.
* Strengthen Synopsys' position as a leader in highspeed interface IP across commercial, enterprise, and automotive markets.
What You'll Need:
* Bachelor's degree in Electrical Engineering (BSEE) with 12+ years of experience, or Master's degree (MSEE) with 10+ years.
* Demonstrated experience as ateam lead or people managerin an ASIC digital design environment.
* Extensive handson ASIC RTL design experience, with direct ownership of complex digital designs.
* Deep expertise in USB digital design and architecture or similar protocols.
* Strong understanding of ASIC design fundamentals including clocking, resets, lowpower techniques, and design for test.
* Experience with AI-driven tools, flows and methodologies. Familiarity with scripting languages (Perl, TCL, Python) for design automation is a plus.
At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.
In addition to the base salary, this role may be eligible for an annual bonus, equity, and other discretionary bonuses. Synopsys offers comprehensive health, wellness, and financial benefits as part of a competitive total rewards package. The actual compensation offered will be based on a number of job-related factors, including location, skills, experience, and education. Your recruiter can share more specific details on the total rewards package upon request. The base salary range for this role is across the U.S.
Sourced by ZipRecruiter
Synopsys, Inc. (Nasdaq:SNPS) is the Silicon to Software partner for creative companies developing the electronic products and software applications we rely on every single day. As the world's 15th largest software company, Synopsys has a long history of being a global leader in electronic design automation (EDA) and semiconductor IP and is also growing its leadership in software quality and security solutions. Whether you're a system-on-chip (SoC) designer building advanced semiconductors, or a software developer writing applications that require the highest quality and security, Synopsys has the solutions needed to deliver exceptional, secure products for the era of connected everything. The company is headquartered in Mountain View, California, and has approximately 113 offices located throughout North America, South America, Europe, Japan, Asia and India. Since 1986, Synopsys has been at the heart of accelerating electronics innovation with engineers around the world having used Synopsys technology to successfully design and create billions of chips and systems that are found in the electronics that people rely on every single day.
Computer and computer peripheral equipment and software wholesalers
10,000+ Employees
Mountain View, CA, US
1986
