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Soc Verification Engineer Jobs in California (NOW HIRING)

Intel

Senior SoC Design Verification Engineer

Folsom, CA

$145K - $177K/yr

About the Role As a Senior SoC Design Verification Engineer , you will lead verification efforts for complex system-on-chip (SoC) designs that enable Intel's next generation of client computing and ...

R3 Tek

Verification Engineer

San Francisco, CA · On-site

$160K/yr

Verification Engineer Location: San Francisco Bay Area, CA Employment Type: Contract Required ... Expertise in CXL (Compute express Link) is good to have Expertise in IP as well as SOC verification ...

HCP ONE LLC

Design Verification Engineer

San Jose, CA · On-site

$159K - $194K/yr

Design Verification Engineer Location: San Jose, CA Experience: 8+ Years Type: Contract Description ... Key Skills Required · 8+ years of Design Verification experience in semiconductor/ASIC/SoC ...

Embtel Inc

Senior Verification Engineer (Remote)

Campbell, CA · On-site

$157K/yr

Senior Verification Engineer Location: Campbell, CA ( 100 % remote considered) Duration: Full Time ... ASIC Verification, SoC Verification, Formal verification. * Develop/write testbench, develop/write ...

R3 Tek

Verification Engineer

San Francisco, CA

$160K/yr

Verification Engineer Location: San Francisco Bay Area, CA Employment Type: Contract /Contract to ... as SOC verification  Perl/shell scripting is a good to have  C/C++ knowledge is good to have ...

Marvell

Staff SoC Verification Engineer

San Diego, CA · On-site

Strong background in SoC verification and test bench development using UVM, System Verilog, C/C++, and DPI. * Strong verification skills, understanding of methodology (object oriented programming ...

Marvell

Sr Staff SoC Verification Engineer

San Diego, CA · On-site

$144K/yr

Strong background in SoC verification and test bench development using UVM, System Verilog, C/C++, and DPI. * Strong verification skills, understanding of methodology (object oriented programming ...

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How much do soc verification engineer jobs pay per year?

As of Aug 18, 2026, the average yearly pay for soc verification engineer in California is $140,752.00, according to ZipRecruiter salary data. Most workers in this role earn between $134,200.00 and $134,200.00 per year, depending on experience, location, and employer.

What is a SoC Verification Engineer?

SoC Verification Engineers are professionals who ensure that System-on-Chip (SoC) designs function as intended before manufacturing. They create and run tests, develop verification plans, and use simulation tools to identify and fix design bugs. Their work is crucial for delivering reliable and high-performance chips used in devices like smartphones, computers, and automotive systems. SoC Verification Engineers collaborate closely with design engineers and use specialized languages and tools such as SystemVerilog, UVM, and simulation platforms.

How does a SoC Verification Engineer typically collaborate with design and firmware teams during the product development cycle?

As a SoC Verification Engineer, you will regularly work alongside design and firmware teams to ensure that the integrated circuits function as intended. Collaboration often involves reviewing design specifications, clarifying requirements, and providing early feedback on testability. During the verification phase, you will coordinate testbench development, share simulation results, and help diagnose issues detected in the design. This close interaction is essential for identifying design bugs early, aligning on functionality, and meeting project milestones efficiently.

What are the key skills and qualifications needed to thrive as a SoC Verification Engineer, and why are they important?

To thrive as a SoC Verification Engineer, you need a solid background in digital design, verification methodologies (such as UVM or SystemVerilog), and a degree in electrical engineering or a related field. Familiarity with simulation tools (e.g., ModelSim, VCS), version control systems, and scripting languages like Python or Perl is typically required. Strong problem-solving, attention to detail, and effective teamwork set outstanding candidates apart. These skills are crucial for ensuring the functionality, reliability, and timely delivery of complex system-on-chip products.

What are popular job titles related to Soc Verification Engineer jobs in California?

For Soc Verification Engineer jobs in California, the most frequently searched job titles are:

What job categories do people searching Soc Verification Engineer jobs in California look for?

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Soc Verification Engineer jobs near you
Infographic showing various Soc Verification Engineer job openings in California as of August 2026, with employment types broken down into 100% Full Time. Highlights an 100% In-person job distribution, with an average salary of $140,752 per year, or $67.7 per hour.

SoC Verification Engineer - NoC / UVM

Advanced Micro Devices, Inc

San Jose, CA • On-site

$145K/yr

Full-time

Re-posted 8 days ago

Advanced Micro Devices rating

8.6

Company rating: 8.6 out of 10

Based on 13 frontline employees who took The Breakroom Quiz

27th of 159 rated electronics manufacturers

Job description

WHAT YOU DO AT AMD CHANGES EVERYTHING
At AMD, our mission is to build great products that accelerate next-generation computing experiences-from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you'll discover the real differentiator is our culture. We push the limits of innovation to solve the world's most important challenges-striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career.
THE ROLE:
The verification team at AMD is looking for a Verification Engineer to lead and contribute on the verification of Network on Chip IPs and Subsystems. The individual will help architect, develop and use simulation and/or formal based verification environments, at block and subsystem level, to prove the functional correctness of Network-On-Chip (NOC) IPs, subsystems and SOC designs.
THE PERSON:
You are a skilled verification engineer with strong expertise in System Verilog and UVM, and a solid understanding of ASIC/SoC verification methodologies. You have experience verifying complex digital designs, ideally including NoC architectures, and are proficient in constraint-random, coverage-driven, and formal verification (SVA). You are analytical, detail-oriented, and collaborative, with the ability to debug complex issues, drive verification closure, and effectively partner with global design and architecture teams while taking ownership of challenging problems.
KEY RESPONSIBILITIES:
  • Lead and Plan verification of complex digital design blocks by fully understanding the architecture and design specifications
  • Interact with architects and design engineers to create a comprehensive verification test plan
  • Design and architect testbenches in System Verilog and UVM to complete verification of the design in an efficient manner
  • Create and enhance constrained-random and/or directed verification environments, and formally verify designs with System Verilog Assertions (SVA) and industry leading formal tools
  • Debug tests with design engineers to deliver functionally correct design blocks
  • Identify and write coverage measures for stimulus quality improvements
  • Perform coverage analysis to identify verification holes and achieve closure on coverage metrics

PREFERRED EXPERIENCE:
  • Experienced with development of UVM, OVM, VMM and/or System Verilog, Verilog test benches and usage of simulation tools/debug environments like Synopsys VCS, Cadence IES to test block level/full chip SOCs and FPGAs.
  • Strong understanding of state of the art of verification techniques, including assertion and coverage-driven verification.
  • Strong understanding of different phases of ASIC and/or full custom chip development is required.
  • Experience in block level NOC (Net work on Chip) verification is a plus.
  • Verification Experience in protocols like AXI3/4, DDR4/5, HBM, PCIe, Processors, Graphics is a plus.
  • Experience as a verification architect, establishing the verification methodology, tools and infrastructure for high-performance FPGAs, SOCs and/or VLSI designs is a plus.
  • Experience with gate level simulation, power verification, reset verification, contention checking, abstraction techniques is a plus.
  • Familiarity with verification management tools as well as understanding of database management particularly as it pertains to regression management is a plus.
  • Experience with formal property checking tools such as Cadence (IEV), Jasper and Synopsys (VC-Formal, Magellan) is a plus.

ACADEMIC CREDENTIALS:
  • Bachelors or Masters degree in computer engineering/Electrical Engineering

This role is not eligible for visa sponsorship.
#LI-EV1
#LI-HYBRID
Benefits offered are described: AMD benefits at a glance.
AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants' needs under the respective laws throughout all stages of the recruitment and selection process.
AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD's "Responsible AI Policy" is available here.
This posting is for an existing vacancy.

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