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Remote Formal Verification Engineer Jobs in California

Meta

ASIC Engineer, Design Verification

Sunnyvale, CA · On-site +1

$114K/yr

ASIC Engineer, Design Verification Responsibilities: * Define and implement block, IP, and SoC ... Apply formal verification and emulation techniques to complement simulation-based approaches and ...

Tenstorrent

$100K - $500K/yr

... engineering teams from early design through tapeout and post-silicon validation. The ideal ... You bring practical expertise with formal verification and large-scale CPU verification ...

Qualcomm

CPU Verification Engineer (RISC-V)

Santa Clara, CA · On-site +1

$159K/yr

As a Design Verification Engineer, you will work with Chip Architects to validate the concepts of ... Formal, Assertions, and Silicon bringup, is helpful. * In-depth knowledge of Micro-processor ...

Meta

ASIC Engineer, Design Verification

Sunnyvale, CA · On-site +1

$146K/yr

Along with traditional simulation, you will use other approaches like Formal and Emulation to ... ASIC Engineer, Design Verification Responsibilities: * Define and implement IP/SoC verification ...

Meta

ASIC Engineer, Design Verification

Sunnyvale, CA · On-site +1

$178K/yr

ASIC Engineer, Design Verification Responsibilities: * Define and implement IP/SoC verification ... Formal, Emulation * Experience in EDA tools and scripting (Python, TCL, Perl, Shell) used to build ...

Tenstorrent

DFT Engineer

Santa Clara, CA · On-site +1

$100K - $500K/yr

This role is remote based out of the United States. We welcome candidates at various experience ... You bring expertise in DFT planning, SoC-level silicon debug, formal verification, and signoff of ...

Tenstorrent

Fabric SOC Architect

Santa Clara, CA · Remote

$100K - $500K/yr

This role is remote, based out of The United States. We welcome candidates at various experience ... Familiarity with ML/AI traffic patterns or formal verification of cache coherence protocols is a ...

Array Labs

Space Systems Engineer

Redwood City, CA · On-site +1

We value rapid testing and iteration over protracted analysis and formal verification: you'll own ... S. commercial remote sensing regulations (NOAA), FCC spectrum licensing processes, and export ...

Array Labs

Space Systems Engineer

Redwood City, CA · On-site +1

$150K - $250K/yr

We value rapid testing and iteration over protracted analysis and formal verification: you'll own ... S. commercial remote sensing regulations (NOAA), FCC spectrum licensing processes, and export ...

Hui Huliau

Structural Engineer

San Diego, CA · On-site +1

... Formal training and relevant experience in in-service engineering, aircraft acquisition, and/or ... Verify. Hui Huliau and its subsidiaries are drug free workplaces.

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Remote Formal Verification Engineer information

What is a remote formal verification engineer?

Remote Formal Verification Engineers are professionals who use mathematical methods to verify the correctness of hardware or software designs, ensuring they meet specified requirements and are free from critical errors. They typically work from home or any location outside a traditional office, collaborating with teams online. Their main tasks include writing formal specifications, developing verification strategies, analyzing results, and reporting on system reliability. This role is essential in industries like semiconductor design, automotive, and aerospace, where system failures can have significant consequences.

What are the key skills and qualifications needed to thrive as a remote formal verification engineer?

To thrive as a Remote Formal Verification Engineer, you need a strong background in digital design, formal verification methodologies, and a relevant degree in computer engineering or a related field. Expertise in formal verification tools (such as JasperGold or Questa Formal), hardware description languages (like Verilog or VHDL), and scripting languages is typically required. Strong problem-solving ability, attention to detail, and effective remote communication skills set top performers apart. These skills ensure the accurate validation of hardware designs, reduce costly errors, and enable efficient collaboration in distributed teams.

How does a remote formal verification engineer typically collaborate with development and design teams across different time zones?

As a Remote Formal Verification Engineer, effective collaboration with development and design teams is critical, especially when working across multiple time zones. Most teams use a combination of asynchronous communication tools (like email, Slack, and project management platforms) and scheduled video meetings to align on goals, clarify verification requirements, and review progress. It's common to document verification plans and results thoroughly so colleagues in other regions can review and contribute. Flexibility in working hours and proactive communication help ensure smooth handoffs and minimize blockers, making remote collaboration productive and efficient.

What is the difference between Remote Formal Verification Engineer vs Remote Hardware Verification Engineer?

AspectRemote Formal Verification EngineerRemote Hardware Verification Engineer
Required CredentialsBachelor's/Master's in Electrical Engineering, Computer Science; certifications in formal methodsBachelor's/Master's in Electrical Engineering, Computer Engineering; certifications in hardware testing
Work EnvironmentDesign and analyze digital systems using formal methods remotelyTest and validate hardware components remotely in lab or simulation environments
Industry UsageSemiconductor, electronics, tech companies focusing on verificationSemiconductor, electronics, hardware manufacturing companies
Search & Comparison IntentOften compared due to similar industry and skills, focusing on verification methods

The Remote Formal Verification Engineer specializes in mathematically proving the correctness of digital systems remotely, while the Remote Hardware Verification Engineer tests and validates hardware components remotely. Both roles require strong technical credentials and are used in similar industries, but they focus on different verification techniques and processes.

What are the most commonly searched types of Formal Verification Engineer jobs in California?

The most popular types of Formal Verification Engineer jobs in California are:

What are popular job titles related to Remote Formal Verification Engineer jobs in California?

For Remote Formal Verification Engineer jobs in California, the most frequently searched job titles are:

What job categories do people searching Remote Formal Verification Engineer jobs in California look for?

The top searched job categories for Remote Formal Verification Engineer jobs in California are:

What cities in California are hiring for Remote Formal Verification Engineer jobs?

Cities in California with the most Remote Formal Verification Engineer job openings:

Remote Formal Verification Engineer jobs near you
Infographic showing various Remote Formal Verification Engineer job openings in California as of August 2026, with employment types broken down into 95% Full Time, 2% Part Time, and 3% Contract. Highlights an 85% Physical, 6% Hybrid, and 9% Remote job distribution.

ASIC Engineer, Design Verification

Sunnyvale, CA • On-site, Remote

Meta
Internet and IT • 10K+ employees

7.8

Company rating: 7.8 out of 10

Based on 45 frontline employees who took The Breakroom Quiz

139th of 246 rated software companies

People enjoy working here

Good employer

Recommended by students

Learn more about Metaexternal

$114K/yr

Full-time

Re-posted 25 days ago

Job description

Meta is hiring an ASIC Design Verification Engineer within the Infrastructure Silicon organization. We are looking for individuals with experience in Design Verification to build IP and System on Chip (SoC) solutions for data center applications.In this role, you will work alongside experienced engineers focused on developing advanced ASIC solutions that power Meta's data center infrastructure. You will own verification closure for design modules or sub-systems, spanning test planning, UVM-based testbench development, and coverage closure. In addition to simulation-based verification, you will leverage formal verification and emulation methodologies to achieve bug-free silicon. This role offers meaningful opportunities to collaborate with full-stack software, hardware, ASIC design, emulation, and post-silicon validation teams toward first-pass silicon success.
ASIC Engineer, Design Verification Responsibilities:
  • Define and implement block, IP, and SoC-level verification plans to enable comprehensive functional coverage across design hierarchies
  • Develop and maintain UVM-based testbenches and functional test sequences aligned to the verification test plan
  • Drive verification closure using defined metrics including functional coverage, code coverage, and assertion coverage
  • Debug and root-cause functional failures in RTL designs, partnering closely with the ASIC design team to resolve issues
  • Apply formal verification and emulation techniques to complement simulation-based approaches and improve verification efficiency
  • Collaborate with design, architecture, and post-silicon validation teams to align on verification goals and ensure design quality
  • Develop reusable verification infrastructure components including scoreboards, monitors, and coverage models
  • Contribute to scripting and automation flows using Python, TCL, or Shell to improve verification productivity and regression management
  • Participate in design reviews and verification planning discussions to identify potential design risks early in the development cycle

Minimum Qualifications:
  • Currently has, or is in the process of obtaining a Bachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience. Degree must be completed prior to joining Meta
  • 2+ years of hands-on experience in SystemVerilog and UVM-based verification methodology or C/C++ based hardware verification
  • 2+ years of experience in block, IP, sub-system, or SoC-level verification using SystemVerilog UVM or OVM methodologies
  • Experience with EDA simulation tools and scripting languages such as Python, TCL, Perl, or Shell for building verification environments and flows
  • Experience debugging RTL functional failures and performing root-cause analysis in a simulation or emulation environment

Preferred Qualifications:
  • Experience with Emulation platform usage for Pre-Si verification
  • Experience verifying ARM or RISC-V based sub-systems or SoCs, or data center application designs such as AI/ML accelerators, networking, or video processing ASICs
  • Experience with IP or integration verification of high-speed interfaces such as PCIe, DDR, or Ethernet
  • Experience developing UVM-based verification environments from scratch, including environment architecture, sequencers, and coverage models
  • Experience with Chip Debug Logic, Telemetry and/or RAS

About Meta:
Meta builds technologies that help people connect, find communities, and grow businesses. When Facebook launched in 2004, it changed the way people connect. Apps like Messenger, Instagram and WhatsApp further empowered billions around the world. Now, Meta is moving beyond 2D screens toward immersive experiences like augmented and virtual reality to help build the next evolution in social technology. People who choose to build their careers by building with us at Meta help shape a future that will take us beyond what digital connection makes possible today—beyond the constraints of screens, the limits of distance, and even the rules of physics.
Meta is proud to be an Equal Employment Opportunity and Affirmative Action employer. We do not discriminate based upon race, religion, color, national origin, sex (including pregnancy, childbirth, or related medical conditions), sexual orientation, gender, gender identity, gender expression, transgender status, sexual stereotypes, age, status as a protected veteran, status as an individual with a disability, or other applicable legally protected characteristics. We also consider qualified applicants with criminal histories, consistent with applicable federal, state and local law. Meta participates in the E-Verify program in certain locations, as required by law. Please note that Meta may leverage artificial intelligence and machine learning technologies in connection with applications for employment.
Meta is committed to providing reasonable accommodations for candidates with disabilities in our recruiting process. If you need any assistance or accommodations due to a disability, please let us know at accommodations-ext@meta.com.
$114,000/year to $172,000/year + bonus + equity + benefits
Individual compensation is determined by skills, qualifications, experience, and location. Compensation details listed in this posting reflect the base hourly rate, monthly rate, or annual salary only, and do not include bonus, equity or sales incentives, if applicable. In addition to base compensation, Meta offers benefits. Learn more about benefits at Meta.

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