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Soc Design Verification Engineer Jobs in California

Redolent, Inc.

Design Verification Engineer

Santa Clara, CA · On-site

$159K - $195K/yr

We are seeking a skilled Design Verification Engineer to join our hardware engineering team. The ... Experience with SoC-level verification , assertion-based verification , or formal verification

iFlow Inc

Design Verification Engineer

Santa Clara, CA · On-site

$159K - $195K/yr

Design Verification Engineer Location:Santa Clara CA Duration: Long term Experience:8-15 Years ... SoC level testing Develop directed and random testcases, perform coverage analysis, and close ...

Apple

PHY Design Verification Engineer

San Francisco, CA · On-site

$160K - $195K/yr

Our wireless SoC organization is responsible for all aspects of wireless silicon development with a ... As a PHY Design Verification Engineer, you will be responsible for pre-silicon RTL verification of ...

Apple

Design Verification Engineer

Cupertino, CA · On-site

$167K - $204K/yr

Design Verification Engineers at Apple are responsible for verifying the functionality and ... You own ensuring the quality of the SOC or an IP or subsystem. This requires you to review design ...

Apple

PHY Design Verification Engineer

San Francisco, CA · On-site

$160K - $195K/yr

Our wireless SoC organization is responsible for all aspects of wireless silicon development with a ... As a PHY Design Verification Engineer, you will be responsible for pre-silicon RTL verification of ...

Apple

Design Verification Engineer

Cupertino, CA · On-site

$167K - $204K/yr

Design Verification Engineers at Apple are responsible for verifying the functionality and ... You own ensuring the quality of the SOC or an IP or subsystem. This requires you to review design ...

Apple

Design Verification Engineer

San Diego, CA · On-site

$144K - $176K/yr

Design Verification Engineers at Apple are responsible for verifying the functionality and ... You own ensuring the quality of the SOC or an IP or subsystem. This requires you to review design ...

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All JobsSoc Design Verification Engineer JobsSoc Design Verification Engineer Jobs in California

Soc Design Verification Engineer information

See California salary details

$104.1K

$147.2K

$164.8K

How much do soc design verification engineer jobs pay per year?

As of Aug 9, 2026, the average yearly pay for soc design verification engineer in California is $147,197.00, according to ZipRecruiter salary data. Most workers in this role earn between $134,200.00 and $163,800.00 per year, depending on experience, location, and employer.

What are some common challenges faced by a SoC Design Verification Engineer during the verification process?

SoC Design Verification Engineers often encounter challenges related to the increasing complexity of modern system-on-chip architectures, such as integrating numerous IP blocks and ensuring robust communication between them. Debugging failures in large-scale simulations and managing tight project deadlines can also be demanding. Additionally, adapting to evolving verification methodologies and tools, as well as collaborating effectively with design and firmware teams to resolve issues quickly, are common aspects of the role. Successful engineers leverage strong problem-solving skills and proactive communication to navigate these challenges.

What are the key skills and qualifications needed to thrive as a SoC Design Verification Engineer, and why are they important?

To thrive as an SoC Design Verification Engineer, you need a solid background in digital design, computer architecture, and verification methodologies, typically supported by a degree in electrical or computer engineering. Familiarity with hardware description languages (HDL) like Verilog or VHDL, verification tools such as UVM/SystemVerilog, and simulation/debugging environments is essential. Strong analytical thinking, problem-solving abilities, and effective communication skills help in collaborating with design teams and troubleshooting complex issues. These skills and qualities are vital to ensure the reliability, functionality, and timely delivery of complex system-on-chip products.

What is a SoC Design Verification Engineer?

SoC (System-on-Chip) Design Verification Engineers are professionals who ensure that integrated circuits, which combine multiple components onto a single chip, function correctly according to their specifications. They use various verification methodologies and tools to simulate, test, and debug the design before it is manufactured. Their work involves creating testbenches, running simulation tests, and collaborating with design engineers to identify and resolve issues early in the development cycle. This helps prevent costly errors and ensures the final product meets quality and performance standards.

What is the difference between Soc Design Verification Engineer vs Soc Validation Engineer?

AspectSoc Design Verification EngineerSoc Validation Engineer
Primary FocusVerifying design correctness through simulation and testing during developmentValidating the final product to ensure it meets specifications and functions in real-world scenarios
Work EnvironmentDesign teams, simulation labs, hardware testingProduct testing, field testing, customer environments
Required CredentialsBachelor's or master's in Electrical Engineering, VLSI, or related fields; knowledge of verification toolsBachelor's or master's in Electrical Engineering, VLSI, or related fields; experience with testing methodologies

The Soc Design Verification Engineer primarily focuses on verifying the design correctness during development, while the Soc Validation Engineer tests the final product to ensure it functions correctly in real-world conditions. Both roles require similar educational backgrounds and industry experience, but their responsibilities differ in the development lifecycle.

What are popular job titles related to Soc Design Verification Engineer jobs in California? For Soc Design Verification Engineer jobs in California, the most frequently searched job titles are:
What job categories do people searching Soc Design Verification Engineer jobs in California look for? The top searched job categories for Soc Design Verification Engineer jobs in California are:
What cities in California are hiring for Soc Design Verification Engineer jobs? Cities in California with the most Soc Design Verification Engineer job openings:
Soc Design Verification Engineer jobs near you
Infographic showing various Soc Design Verification Engineer job openings in California as of July 2026, with employment types broken down into 70% Full Time, and 30% Contract. Highlights an 90% In-person, and 10% Remote job distribution, with an average salary of $147,197 per year, or $70.8 per hour.

Principal Design Verification Engineer

Bolt Graphics

Sunnyvale, CA • On-site

$250K - $280K/yr

Full-time

Medical, Dental, Vision, Retirement

Re-posted 25 days ago

Job description

Bolt Graphics is a semiconductor startup based in Sunnyvale, CA building the fastest and most efficient graphics processors. We pride ourselves on our first principles approach to solving problems. We are energized by our mission to reduce the barrier of entry for content creation and consumption. Our goal is to enable everyone to easily create, simulate and consume immersive experiences as vividly as they can imagine them.
Our Values
  • Be Fearless: Unmute yourself. Test boundaries and get proven right.
  • Remain Adaptable: Stay comfortable in a continuously changing world. If you're wrong, concede and move on.
  • Educate Your Ego: Selflessly collaborate towards our shared purpose.

About the role:
As a Principal Design Verification Engineer, you will own the verification strategy and execution for complex IPs or full-chip SoC. You will lead a team of verification engineers, define methodologies, drive coverage closure, and ensure high-quality silicon delivery. This is an on-site role and will require presence in the office 5 days a week. No hybrid option is available.
What you'll do:
Leadership & Strategy
  • Define and drive end-to-end verification strategy (block → subsystem → full-chip)
  • Build, mentor, and scale a high-performing DV team
  • Establish verification plans, milestones, and coverage goals
  • Drive alignment across architecture, RTL, and physical design teams

Verification Execution
  • Lead development of UVM-based verification environments
  • Define testbench architecture, stimulus strategy, and reusable components
  • Drive functional, code, and assertion coverage closure
  • Oversee regression infrastructure, debug, and signoff criteria

Advanced Verification & Signoff
  • Drive GLS (Gate-Level Simulation) with SDF annotation and timing-aware debug
  • Manage low-power verification (UPF/CPF) and power-aware simulation
  • Oversee formal verification, linting, CDC/RDC analysis
  • Ensure robust reset, clocking, and cross-domain verification

Cross-Functional Collaboration
  • Work with RTL teams on design-for-verification (DFV) improvements
  • Collaborate with PD teams on timing-related verification issues
  • Support post-silicon bring-up and debug
  • Interface with customers/partners on verification readiness and quality

Required Qualifications:
  • Bachelor's/Master's degree in Electrical Engineering or related field
  • 12-15 years of experience in ASIC/SoC design verification
  • Proven experience leading verification teams and delivering multiple tapeouts
  • Strong expertise in:
    • SystemVerilog and UVM methodology
    • Functional coverage, assertions (SVA), and constrained-random verification
    • Debugging complex SoC-level issues
  • Hands-on experience with industry-standard tools such as:
    • Synopsys VCS / Cadence Xcelium
    • Synopsys Verdi
  • Strong understanding of:
    • Clock/reset domain crossings (CDC/RDC)
    • Low-power verification methodologies
    • Gate-level simulation and SDF annotation
  • Excellent leadership, communication, and problem-solving skills

Preferred Qualifications:
  • Experience in CPU/GPU/AI/Networking SoCs
  • Expertise in GLS debug (X-propagation, SDF issues, timing failures)
  • Familiarity with emulation platforms (e.g., Synopsys ZeBu)
  • Experience with post-silicon validation and bring-up
  • Knowledge of performance verification and system-level validation
  • Strong scripting skills (Python/TCL) for automation and regression scaling

Compensation Range: $250,000-$280,000 per year (California). This range represents the anticipated base pay for this role based in California; the final offer may vary based on qualifications, experience, and location.
Benefits:
  • Medical, Dental, & Vision - 100% covered premiums
  • Equity - Stock Options
  • 401(k) match
  • WFH Hardware

Bolt is committed to building a diverse and inclusive environment in which we recognize and value each other's differences as well as fostering a culture that promotes its core values: Professionalism, Integrity, and Respect. As an equal opportunity employer, all qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, genetic information, national origin, age, disability, or status as a protected veteran.

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