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Senior Physical Design Engineer Jobs (NOW HIRING)

Senior Physical Design Engineer(7051)

San Jose, CA · On-site

$155K - $160K/yr

Overview of Role As a Senior Physical Design Engineer, you will be responsible for the physical design implementation PnR run, Performance/Power/Area (PPA) comparison, congestion & DRC analysis, and ...

Senior Physical Design Engineer(7051)

San Jose, CA · Hybrid

$155K - $160K/yr

Overview of Role As a Senior Physical Design Engineer, you will be responsible for the physical design implementation PnR run, Performance/Power/Area (PPA) comparison, congestion & DRC analysis, and ...

About the Role Altera is seeking a highly motivated Senior Physical Design Engineer to join our Physical Design organization. In this role, you will be responsible for implementing custom IP and SoC ...

About the Role Altera is seeking a highly motivated Senior Physical Design Engineer to join our Physical Design organization. In this role, you will be responsible for implementing custom IP and SoC ...

New

About the Role As a Physical Design Engineer at Altera, you will play a critical role in our backend implementation flow - from RTL/netlist through to GDSII/tape-out for FPGA/SoC devices. You will ...

Senior Physical Design Engineer Sunnyvale, CA, USA Fulltime Visa- G C and U S C Only We are looking for a Senior Physical Design Engineer with 8-14 years of experience to lead and execute RTL to ...

We are seeking a highly skilled Senior Physical Design Engineer to work on the implementation of complex digital blocks. In this role, you will leverage your expertise in advanced process nodes (3nm ...

Showing results 41-60

Senior Physical Design Engineer information

See salary details

$70.5K

$134.6K

$195K

How much do senior physical design engineer jobs pay per year?

As of Aug 14, 2026, the average yearly pay for senior physical design engineer in the United States is $134,577.00, according to ZipRecruiter salary data. Most workers in this role earn between $107,500.00 and $157,500.00 per year, depending on experience, location, and employer.

What are some common challenges faced by senior physical design engineers during the chip tape-out phase?

Senior Physical Design Engineers often encounter tight deadlines and last-minute design changes during the chip tape-out phase, which can make ensuring timing closure and meeting power, performance, and area (PPA) targets particularly challenging. Collaborating closely with verification and layout teams is essential to quickly resolve any critical design rule violations or integration issues. Effective communication, attention to detail, and thorough knowledge of EDA tools are key to successfully managing these high-pressure situations and delivering a manufacturable design on schedule.

What is a senior physical design engineer?

A Senior Physical Design Engineer is a highly skilled professional in the field of semiconductor engineering who specializes in transforming circuit designs (netlists) into physical layouts for integrated circuits (ICs). They are responsible for tasks such as floorplanning, placement, clock tree synthesis, and routing, ensuring that the chip meets performance, area, and power requirements. Senior engineers in this role often lead projects, mentor junior engineers, and collaborate closely with other design and verification teams to deliver high-quality silicon products.

What is the difference between Senior Physical Design Engineer vs Physical Design Engineer?

AspectSenior Physical Design EngineerPhysical Design Engineer
Required CredentialsBachelor's or Master's in Electrical Engineering or Computer Engineering; experience in physical design toolsBachelor's or Master's in Electrical Engineering or Computer Engineering; entry to mid-level experience
Work EnvironmentDesign teams in semiconductor or chip design companies, using EDA toolsDesign teams in semiconductor or chip design companies, using EDA tools
Employer & Industry UsageCommonly employed in advanced chip design companies, focusing on complex ICsUsed across various semiconductor companies for standard physical design tasks

The main difference is experience level and responsibility. Senior Physical Design Engineers typically lead complex projects and mentor junior staff, while Physical Design Engineers focus on executing design tasks under supervision. Both roles require similar technical skills and work in similar environments, but the senior role involves more leadership and strategic planning.

What are the key skills and qualifications needed to thrive as a senior physical design engineer?

To thrive as a Senior Physical Design Engineer, you need expertise in VLSI design, ASIC/SoC implementation, and a solid background in electrical or computer engineering, often complemented by a relevant degree. Mastery of EDA tools such as Cadence, Synopsys, or Mentor Graphics, and familiarity with scripting languages like TCL and Python, is typically required. Strong problem-solving abilities, attention to detail, and effective communication are critical soft skills for collaborating with cross-functional teams and managing complex projects. These skills and qualifications ensure efficient, high-quality chip design, meeting both technical and timeline requirements in a competitive industry.

How much does a senior physical design engineer make in the US?

A senior physical design engineer in the US typically earns between $110,000 and $160,000 annually, depending on experience, location, and company size. Compensation may also include bonuses and stock options, especially in high-tech industries or large corporations.
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What cities are hiring for Senior Physical Design Engineer jobs?

Cities with the most Senior Physical Design Engineer job openings:

What are the most commonly searched types of Physical Design Engineer jobs?

The most popular types of Physical Design Engineer jobs are:

What states have the most Senior Physical Design Engineer jobs?

States with the most job openings for Senior Physical Design Engineer jobs include:

Infographic showing various Senior Physical Design Engineer job openings in the United States as of August 2026, with employment types broken down into 1% As Needed, 76% Full Time, 18% Part Time, 1% Temporary, 3% Contract, and 1% Nights. Highlights an 98% Physical, 1% Hybrid, and 1% Remote job distribution, with an average salary of $134,577 per year, or $64.7 per hour.

Senior Physical Design Engineer

United Airlines

Santa Clara, CA

$82K - $193K/yr

Full-time

Medical, Dental, Vision, Life, Retirement, PTO

Posted 9 days ago


United Airlines rating

7.9

Company rating: 7.9 out of 10

Based on 342 frontline employees who took The Breakroom Quiz

7th of 26 rated airlines


Job description

At Capgemini Engineering, the world leader in engineering services, we bring together a global team of engineers, scientists, and architects to help the world's mostinnovative companies unleash their potential. From autonomous cars to life-saving robots, our digital and software technology experts think outside the box as theyprovide unique R&D and engineering services across all industries. Join us for a career full of opportunities. Where you can make a difference. Where no two days arethe same.

Location

This is an onsite role based in Santa Clara, CA.

About the job you're considering

As a Physical Design Engineer, you will work on complex digital and mixed-signal designs across advanced process technologies, helping drive designs from implementation through verification and tape-out. This role offers the opportunity to solve challenging physical design problems, collaborate with cross-functional engineering teams, and support next-generation IC product development using industry-leading methodologies and tools.

Your role

As a Physical Design Engineer, you will support the implementation and optimization of advanced-node semiconductor designs. Key responsibilities may include:

  • Lead or support physical design activities, including floor planning, placement, clock tree synthesis, routing, and physical-aware synthesis.
  • Develop and implement power-grid strategies, high-speed clock constraints, and design specifications to support performance, power, and area goals.
  • Perform physical design verification and debug LVS and DRC issues at both chip and block levels.
  • Collaborate with design, layout, verification, timing, and methodology teams to address implementation challenges across the design lifecycle.
  • Support CDC, static timing analysis, parasitic-aware simulation, and timing closure activities using relevant EDA tools and methodologies.
  • Contribute to tape-out readiness, including design signoff, foundry interaction, and alignment with IC product development requirements.
  • Evaluate design tradeoffs related to power consumption, area, performance, layout complexity, and technology limitations for advanced process nodes(3nm /5nm/7nm
Your skills and experience

We are looking for candidates with strong physical design expertise and hands-on experience in advanced semiconductor implementation. Ideal qualifications include:

  • Must have 10+ years of experience in Physical Design, with hands-on expertise supporting complex digital or mixed-signal IC implementation.
  • Strong knowledge of physical design flows, including floor planning, clock tree synthesis, place and route, physical-aware synthesis, and design closure.
  • Experience developing power-grid strategies and high-speed clock constraints to support performance, power, and area goals.
  • Working knowledge of physical verification methodologies, including LVS and DRC debug at chip and block levels.
  • Familiarity with CDC, static timing analysis methodologies, SDF-annotated simulations, and parasitic delay impact.
  • Exposure to mixed-signal design environments and the interaction between digital implementation and analog/layout requirements.
  • Hands-on experience with tools such as Virtuoso, Calibre, RedHawk, or similar EDA platforms.
  • Understanding of design tape-out processes, foundry requirements, and the semiconductor product development supply chain.
  • Experience with advanced TSMC process nodes, such as 7nm through 2nm, is highly preferred.

Preferred qualifications

  • Experience estimating design and layout effort for digital blocks in advanced-node technologies.
  • Strong understanding of power, performance, and area tradeoffs in leading-edge process technologies.
  • Prior experience supporting full-chip or block-level tape-out to foundries.
  • Ability to work collaboratively across multiple engineering disciplines and communicate technical tradeoffs clearly.

The base compensation range for this role in the posted location is: $82,082 to $193,440

Capgemini provides compensation range information in accordance with applicable national, state, provincial, and local pay transparency laws. The base compensation range listed for this position reflects the minimum and maximum target compensation Capgemini, in good faith, believes it may pay for the role at the time of this posting. This range may be subject to change as permitted by law.

The actual compensation offered to any candidate may fall outside of the posted range and will be determined based on multiple factors legally permitted in the applicable jurisdiction.

These may include, but are not limited to: Geographic location, Education and qualifications, Certifications and licenses, Relevant experience and skills, Seniority and performance, Market and business consideration, Internal pay equity.

It is not typical for candidates to be hired at or near the top of the posted compensation range.

In addition to base salary, this role may be eligible for additional compensation such as variable incentives, bonuses, or commissions, depending on the position and applicable laws.

Capgemini offers a comprehensive, non-negotiable benefits package to all regular, full-time employees. In the U.S. and Canada, available benefits are determined by local policy and eligibility and may include: 

  • Paid time off based on employee grade (A-F), defined by policy: Vacation: 12-25 days, depending on grade, Company paid holidays, Personal Days, Sick Leave
  • Medical, dental, and vision coverage (or provincial healthcare coordination in Canada)
  • Retirement savings plans (e.g., 401(k) in the U.S., RRSP in Canada)
  • Life and disability insurance
  • Employee assistance programs
  • Other benefits as provided by local policy and eligibility

Important Notice: Compensation (including bonuses, commissions, or other forms of incentive pay) is not considered earned, vested, or payable until it becomes due under the terms of applicable plans or agreements and is subject to Capgemini's discretion, consistent with applicable laws. The Company reserves the right to amend or withdraw compensation programs at any time, within the limits of applicable legislation.

Disclaimers

Capgemini is an Equal Opportunity Employer encouraging inclusion in the workplace. Capgemini also participates in the Partnership Accreditation in Indigenous Relations (PAIR) program which supports meaningful engagement with Indigenous communities across Canada by promoting fairness, accessibility, inclusion and respect.  We value the rich cultural heritage and contributions of Indigenous Peoples and actively work to create a welcoming and respectful environment. All qualified applicants will receive consideration for employment without regard to race, national origin, gender identity/expression, age, religion, disability, sexual orientation, genetics, veteran status, marital status or any other characteristic protected by law.

This is a general description of the Duties, Responsibilities and Qualifications required for this position. Physical, mental, sensory or environmental demands may be referenced in an attempt to communicate the manner in which this position traditionally is performed. Whenever necessary to provide individuals with disabilities an equal employment opportunity, Capgemini will consider reasonable accommodations that might involve varying job requirements and/or changing the way this job is performed, provided that such accommodation does not pose an undue hardship. Capgemini is committed to providing reasonable accommodation during our recruitment process. If you need assistance or accommodation, please reach out to your recruiting contact.

Please be aware that Capgemini may capture your image (video or screenshot) during the interview process and that image may be used for verification, including during the hiring and onboarding process.

Click the following link for more information on your rights as an Applicant in the United States.  http://www.capgemini.com/resources/equal-employment-opportunity-is-the-law

Capgemini is a global business and technology transformation partner, helping organizations to accelerate their dual transition to a digital and sustainable world, while creating tangible impact for enterprises and society. It is a responsible and diverse group of 340,000 team members in more than 50 countries. With its strong over 55-year heritage, Capgemini is trusted by its clients to unlock the value of technology to address the entire breadth of their business needs. It delivers end-to-end services and solutions leveraging strengths from strategy and design to engineering, all fueled by its market leading capabilities in AI, generative AI, cloud and data, combined with its deep industry expertise and partner ecosystem.


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About United Airlines

Sourced by ZipRecruiter

United Airlines is embarking on an exciting journey to become the best airline in aviation history. Our purpose, "Connecting People, Uniting the World," extends beyond transportation, emphasizing our commitment to uplift and create opportunities in the places we serve. With a global presence and diverse workforce, we value inclusivity and are dedicated to hiring tens of thousands of individuals across various roles. Our comprehensive benefits package, including perks like space available travel, parental leave, and 401k, aims to support your well-being and growth.

Industry

Aviation

Company size

10,000+ Employees

Headquarters location

Chicago, IL, US

Year founded

1926

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