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Senior Ic Layout Engineer Jobs (NOW HIRING)

Saige Partners

Analog Layout Engineer

San Jose, CA · On-site

$100 - $110/hr

Senior High-Speed Mixed-Signal / Analog IC Layout Engineer (San Jose, CA) As an Analog Layout Engineer, you will be responsible for: Layout of Analog / High Speed transceiver circuit blocks such as ...

IC Enable

IC Layout Design Engineer

Richardson, TX · Hybrid

  • Medical

  • Dental

  • Vision

  • Retirement

The team has an exciting opportunity for a IC Layout Design Engineer V to join our diverse team executing full-custom integrated circuit development with specific responsibility for driving the ...

Glow Networks

Analog Layout Engineer

Santa Clara, CA · On-site

$237K/yr

Senior layout designer, will be responsible for layout of high-performance analog cores such as ... Responsibilities include leading IC layout of cutting-edge high-performance, high-speed CMOS ...

Falcomm

Senior RFIC Layout Engineer

Atlanta, GA · On-site

$100K - $138K/yr

  • Medical

  • Dental

  • Vision

  • Retirement

  • PTO

Falcomm is seeking a Senior RFIC Layout Engineer to support the physical implementation of RF and ... This role focuses on developing high-quality IC layouts for RF front-end circuits while ensuring ...

Falcomm

Senior RFIC Layout Engineer

Atlanta, GA · On-site

$100K - $138K/yr

  • Medical

  • Dental

  • Vision

  • Retirement

  • PTO

Falcomm is seeking a Senior RFIC Layout Engineer to support the physical implementation of RF and ... This role focuses on developing high-quality IC layouts for RF front-end circuits while ensuring ...

Skyworks

Sr. Principal IC Layout Designer

Greensboro, NC · On-site

$114K - $220K/yr

  • Medical

  • Retirement

  • PTO

Partner with senior analog/RFIC layout engineers to design cellular-band RFICs, including LNAs, RF ... Develop and maintain the IC layout methodology roadmap, collaborating with technology, CAD, and ...

Falcomm

Senior RFIC Layout Engineer

Atlanta, GA · On-site

$100K - $138K/yr

  • Medical

  • Dental

  • Vision

  • Retirement

  • PTO

Falcomm is seeking a Senior RFIC Layout Engineer to support the physical implementation of RF and ... This role focuses on developing high-quality IC layouts for RF front-end circuits while ensuring ...

Teledyne

Senior IC Design Engineer

Chestnut Ridge, NY

$141K - $189K/yr

Layout support will be available, but the Senior IC Designer is responsible for overseeing the ... Electrical Engineering * Thorough understanding of fundamental circuit design concepts such as ...

Impinj

Senior Staff Design Engineer, IC Layout

$158K - $238K/yr

  • Medical

  • Retirement

The Layout Design Engineering group is an integral part of the Silicon Engineering department, working closely with the analog RFID end-point IC development team and the Reader IC team ...

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Senior Ic Layout Engineer information

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$59.5K

$126.6K

$183.5K

How much do senior ic layout engineer jobs pay per year?

As of Aug 16, 2026, the average yearly pay for senior ic layout engineer in the United States is $126,557.00, according to ZipRecruiter salary data. Most workers in this role earn between $104,500.00 and $143,500.00 per year, depending on experience, location, and employer.

What are the key skills and qualifications needed to thrive as a senior IC layout engineer?

To thrive as a Senior IC Layout Engineer, you need expertise in analog and digital IC layout, deep understanding of semiconductor process technologies, and typically a degree in electrical engineering or a related field. Proficiency in layout design tools such as Cadence Virtuoso, familiarity with DRC/LVS verification tools, and knowledge of industry standards are essential. Strong attention to detail, problem-solving skills, and effective communication help ensure collaboration with design and verification teams. These competencies are crucial for creating high-performance, manufacturable integrated circuits that meet rigorous quality and reliability standards.

What is the difference between Senior IC Layout Engineer vs IC Design Engineer?

AspectSenior IC Layout EngineerIC Design Engineer
Primary FocusPhysical layout, placement, routing of integrated circuitsCircuit design, schematic development, functional verification
Skills & CertificationsEDA tools, layout best practices, design rulesCircuit theory, HDL languages, simulation tools
Work EnvironmentFoundries, semiconductor companies, design housesDesign firms, semiconductor companies, R&D labs

While both roles collaborate closely in chip development, the Senior IC Layout Engineer specializes in the physical implementation of circuits, focusing on layout and fabrication constraints. In contrast, the IC Design Engineer concentrates on creating and verifying circuit functionality at the schematic level. Both roles require strong technical skills but differ in their core responsibilities within the chip design process.

What is a senior IC layout engineer?

Senior IC Layout Engineers are specialized professionals who design and implement the physical layout of integrated circuits (ICs) on semiconductor chips. They translate circuit schematics into detailed geometric representations that can be fabricated onto silicon wafers. Their role involves ensuring optimal placement of components, routing of interconnections, and compliance with design rules to achieve desired performance, power, and area targets. Senior engineers typically have advanced experience, oversee complex projects, and may mentor junior team members. They play a critical role in the development of high-performance electronics used in various industries.

What are the main challenges senior IC layout engineers face when working on complex analog or mixed-signal designs?

Senior IC Layout Engineers often encounter challenges related to meeting stringent design specifications, such as minimizing parasitic effects, ensuring signal integrity, and optimizing area usage. Managing multiple iterations with circuit designers and verification teams to address performance and reliability concerns can be demanding, especially under tight project timelines. Additionally, staying updated with evolving EDA tools and process technologies is essential for maintaining productivity and delivering high-quality layouts.

What cities are hiring for Senior Ic Layout Engineer jobs?

Cities with the most Senior Ic Layout Engineer job openings:

What are the most commonly searched types of Ic Layout Engineer jobs?

The most popular types of Ic Layout Engineer jobs are:

What states have the most Senior Ic Layout Engineer jobs?

States with the most job openings for Senior Ic Layout Engineer jobs include:

Senior Ic Layout Engineer jobs near you
Infographic showing various Senior Ic Layout Engineer job openings in the United States as of August 2026, with employment types broken down into 92% Full Time, 2% Part Time, and 6% Contract. Highlights an 86% Physical, 5% Hybrid, and 9% Remote job distribution, with an average salary of $126,557 per year, or $60.8 per hour.

Analog Layout Engineer

Saige Partners

San Jose, CA • On-site

$100 - $110/hr

Full-time

Posted 13 days ago

Job description

Job Description We strive to be Your Future, Your Solution to accelerate your career. Contact Christine Gonzalez at cgonzalez@saigpartners.com, you can also schedule an appointment, to learn more about this opportunity. Senior High-Speed Mixed-Signal / Analog IC Layout Engineer (San Jose, CA) As an Analog Layout Engineer, you will be responsible for: Layout of Analog / High Speed transceiver circuit blocks such as amplifiers, drivers, ADC, DAC, LDO, PLL, filters, etc

in a timely manner. Layout of sensitive active / passive components including resistors, capacitors and inductors. Design verification including DRC, LVS, ERC and ANT and extraction.

Block level floor planning with design engineers. Review and update layout for quality including signal integrity, power integrity and parasitic. Requirements: Associate degree or above with formal training in custom analog layout; BSEE or above preferred The ideal candidate will have the following qualifications: 5+ years analog layout experience in deep sub-micron and FinFET processes.

Experience in floor planning and layout of analog blocks such as amplifiers, drivers, ADC, DAC, LDO, PLL, filters, etc. Solid knowledge in device structures. Understand tradeoffs in matching, coupling, parasitic effects, area, etc.

Understand causes and preventions of ESD and latch-up. Proficient in interpreting verification DRC, LVS, ERC, ANT results. Working knowledge of Cadence Virtuoso and Mentor Calibre required.

Team player with excellent communication skills. Saige Partners, one of the fastest growing technology and talent companies in the Midwest, believes in people with a passion to help them succeed. We are in the business of helping professionals Build Careers, Not Jobs.

Saige Partners believes employees are the most valuable asset to building a thriving and successful company culture. Contact us to learn more about the opportunity below or check out other opportunities at https://careers.saigepartners.com/.

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