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Afternoon Ic Layout Engineer Jobs (NOW HIRING)

SRI International

IC Layout Engineer III

Princeton, NJ · On-site

$92K - $122K/yr

Overview SRI International (formerly Sarnoff Corporation) is looking for a capable IC Layout Engineer in our Princeton, NJ office. The successful candidate will be presented with challenges in IC ...

SRI International

IC Layout Engineer III

Princeton, NJ

$92K - $122K/yr

SRI International (formerly Sarnoff Corporation) is looking for a capable IC Layout Engineer in our Princeton, NJ office. The successful candidate will be presented with challenges in IC Layout and ...

SRI International

IC Layout Engineer III

Princeton, NJ · On-site

$92K - $122K/yr

Overview SRI International (formerly Sarnoff Corporation) is looking for a capable IC Layout Engineer in our Princeton, NJ office. The successful candidate will be presented with challenges in IC ...

Technical Link

Layout - TSMC 3n

Mountain View, CA · On-site

You'll create high-quality, manufacturable analog layouts, collaborate with design engineers, and ensure designs meet electrical and DRC/LVS requirements. Requirements: Proven analog IC layout ...

MediaTek Research Lab Inc.

IC Layout engineer

Irvine, CA · On-site

$85.90 - $137.50/hr

Position Analog Layout Engineer, Analog Design and Circuit Technology, Irvine, California. Responsibilities * Work closely with the design team to develop high‑quality layouts for product ...

IC Enable

IC Layout Design Engineer

Richardson, TX · Hybrid

The team has an exciting opportunity for a IC Layout Design Engineer V to join our diverse team executing full-custom integrated circuit development with specific responsibility for driving the ...

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Afternoon Ic Layout Engineer information

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$45K

$120.8K

$185.5K

How much do afternoon ic layout engineer jobs pay per year?

As of Aug 28, 2026, the average yearly pay for afternoon ic layout engineer in the United States is $120,849.00, according to ZipRecruiter salary data. Most workers in this role earn between $90,000.00 and $144,000.00 per year, depending on experience, location, and employer.

What is the difference between Afternoon Ic Layout Engineer vs Digital IC Design Engineer?

AspectAfternoon IC Layout EngineerDigital IC Design Engineer
Primary FocusPhysical layout and placement of integrated circuitsDesign and architecture of digital circuits and logic
Required SkillsEDA tools, layout optimization, fabrication process knowledgeHDL coding, circuit design, simulation
Work EnvironmentFoundries, semiconductor companies, EDA tool developmentDesign firms, semiconductor companies, research labs
Common CertificationsEDA tool proficiency, semiconductor manufacturing knowledgeVLSI design certifications, HDL proficiency

Afternoon IC Layout Engineers focus on the physical implementation of integrated circuits, ensuring optimal placement and routing. In contrast, Digital IC Design Engineers concentrate on designing the digital logic and architecture. Both roles require knowledge of semiconductor processes and often work closely in the chip development process, but their core responsibilities differ significantly.

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Afternoon Ic Layout Engineer jobs near you
Infographic showing various Afternoon Ic Layout Engineer job openings in the United States as of August 2026, with employment types broken down into 94% Full Time, 2% Part Time, and 4% Contract. Highlights an 85% Physical, 5% Hybrid, and 10% Remote job distribution, with an average salary of $120,849 per year, or $58.1 per hour.

Analog IC Layout Engineer

South San Francisco, CA

Neuralink
Biotechnology Research and Development • 201 - 500 employees
Learn more about Neuralinkexternal

Full-time

Re-posted yesterday

Job description

Team Description:

The Brain Interfaces Soc Department delivers chip architecture and silicon implementation of neural recording and stimulation system-on-chip (SoC) for high-bandwidth brain-computer interfaces. We have crafted a team of exceptional engineers whose mission is to push the frontiers of what is possible today and define the future.

Job Description and Responsibilities:

We are looking for experienced and hands-on engineers with a creative and initiative mindset, who are interested in exploring the next-generation chip design with advanced architectures and hardware accelerators with a goal of enhancing the energy efficiency, information entropy, and scalability of our wireless brain-computer interfaces towards the physical limit of silicon technology. The ideal candidates are energetic people who get excited about building things, are highly analytical, and enjoy tackling new problems. You will have the opportunity to collaborate closely with chip designers, electrical engineers, algorithms engineers, and software engineers on a small, agile team. As an Analog IC Layout Engineer, your responsibilities will include:

  • Crafting state-of-the-art layouts for mixed-signal and analog circuits
    • Amplifiers
    • Filters
    • Switched capacitor circuits
    • Oscillators
    • Data converters
    • Power management circuits
  • Reviewing layout floorplans and analyzing high-fidelity circuits with circuit engineers
  • Physical verification of custom IC mask layouts (LVS, DRC, ERC)

Required Qualifications:

  • Bachelor of Science in Computer Engineering or related field
  • 2+ years of experience in analog and mixed-signal IC layout design
  • 1+ year experience with FinFET technologies
  • Ability to identify the best approach to solving problems

Preferred Qualifications:

  • Programming/scripting knowledge in SKILL, TCL, Shell, C/C++, and/or Python
  • Proven expertise in implementing analog and mixed-signal layout designs, achieving tight matching, low noise, and low power consumption
  • Understanding on failure-prone circuit and layout structures
  • Experience with analog DFM standards
  • Experience with layout P-cell design and implementation
  • Experience with layout automation 

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