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Internship Ic Layout Engineer Jobs (NOW HIRING)

SRI International

IC Layout Engineer III

Princeton, NJ

$92K - $122K/yr

Overview SRI International (formerly Sarnoff Corporation) is looking for a capable IC Layout Engineer in our Princeton, NJ office. The successful candidate will be presented with challenges in IC ...

SRI International

IC Layout Engineer III

Princeton, NJ · On-site

$92K - $122K/yr

SRI International (formerly Sarnoff Corporation) is looking for a capable IC Layout Engineer in our Princeton, NJ office. The successful candidate will be presented with challenges in IC Layout and ...

SRI International

IC Layout Engineer III

Princeton, NJ · On-site

$92K - $122K/yr

Overview SRI International (formerly Sarnoff Corporation) is looking for a capable IC Layout Engineer in our Princeton, NJ office. The successful candidate will be presented with challenges in IC ...

Technical Link

Layout - TSMC 3n

Mountain View, CA · On-site

You'll create high-quality, manufacturable analog layouts, collaborate with design engineers, and ensure designs meet electrical and DRC/LVS requirements. Requirements: Proven analog IC layout ...

MediaTek Research Lab Inc.

IC Layout engineer

Irvine, CA · On-site

$85.90 - $137.50/hr

Position Analog Layout Engineer, Analog Design and Circuit Technology, Irvine, California. Responsibilities * Work closely with the design team to develop high‑quality layouts for product ...

IC Enable

IC Layout Design Engineer

Richardson, TX · Hybrid

The team has an exciting opportunity for a IC Layout Design Engineer V to join our diverse team executing full-custom integrated circuit development with specific responsibility for driving the ...

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Internship Ic Layout Engineer information

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How much do internship ic layout engineer jobs pay per hour?

As of Aug 27, 2026, the average hourly pay for internship ic layout engineer in the United States is $19.31, according to ZipRecruiter salary data. Most workers in this role earn between $16.11 and $20.91 per hour, depending on experience, location, and employer.

What is the difference between Internship Ic Layout Engineer vs Internship Digital IC Design Engineer?

AspectInternship Ic Layout EngineerInternship Digital IC Design Engineer
Primary FocusPhysical layout and fabrication of integrated circuitsDesign and simulation of digital circuit architectures
Skills RequiredLayout tools, CMOS fabrication, circuit design basicsHDL coding, digital logic, simulation tools
Work EnvironmentFoundries, chip design companies, R&D labsSemiconductor companies, design firms, R&D labs
Common CertificationsNone specific, basic electronics knowledgeNone specific, digital design fundamentals

Internship Ic Layout Engineer roles focus on physical design and layout of integrated circuits, working closely with fabrication processes. In contrast, Internship Digital IC Design Engineers concentrate on digital logic design and simulation. Both internships are common in semiconductor industries and require foundational electronics knowledge, but they emphasize different aspects of chip development.

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Internship Ic Layout Engineer jobs near you
Infographic showing various Internship Ic Layout Engineer job openings in the United States as of August 2026, with employment types broken down into 94% Full Time, 2% Part Time, and 4% Contract. Highlights an 85% Physical, 5% Hybrid, and 10% Remote job distribution, with an average salary of $40,174 per year, or $19.3 per hour.

Analog IC Layout Engineer

Neuralink

South San Francisco, CA • On-site

$83K - $139K/yr

Full-time

Medical, Dental, Vision, Retirement

Re-posted 29 days ago

Job description

About Neuralink:
We are creating devices that enable a bi-directional interface with the brain. These devices allow us to restore movement to the paralyzed, restore sight to the blind, and revolutionize how humans interact with their digital world.
Team Description:
The Brain Interfaces Soc Department delivers chip architecture and silicon implementation of neural recording and stimulation system-on-chip (SoC) for high-bandwidth brain-computer interfaces. We have crafted a team of exceptional engineers whose mission is to push the frontiers of what is possible today and define the future.
Job Description and Responsibilities:
We are looking for experienced and hands-on engineers with a creative and initiative mindset, who are interested in exploring the next-generation chip design with advanced architectures and hardware accelerators with a goal of enhancing the energy efficiency, information entropy, and scalability of our wireless brain-computer interfaces towards the physical limit of silicon technology. The ideal candidates are energetic people who get excited about building things, are highly analytical, and enjoy tackling new problems. You will have the opportunity to collaborate closely with chip designers, electrical engineers, algorithms engineers, and software engineers on a small, agile team. As an Analog IC Layout Engineer, your responsibilities will include:
  • Crafting state-of-the-art layouts for mixed-signal and analog circuits
    • Amplifiers
    • Filters
    • Switched capacitor circuits
    • Oscillators
    • Data converters
    • Power management circuits
  • Reviewing layout floorplans and analyzing high-fidelity circuits with circuit engineers
  • Physical verification of custom IC mask layouts (LVS, DRC, ERC)

Required Qualifications:
  • Bachelor of Science in Computer Engineering or related field
  • 2+ years of experience in analog and mixed-signal IC layout design
  • 1+ year experience with FinFET technologies
  • Ability to identify the best approach to solving problems

Preferred Qualifications:
  • Programming/scripting knowledge in SKILL, TCL, Shell, C/C++, and/or Python
  • Proven expertise in implementing analog and mixed-signal layout designs, achieving tight matching, low noise, and low power consumption
  • Understanding on failure-prone circuit and layout structures
  • Experience with analog DFM standards
  • Experience with layout P-cell design and implementation
  • Experience with layout automation

Expected Compensation:
The anticipated base salary for this position is expected to be within the following range. Your actual base pay will be determined by your job-related skills, experience, and relevant education or training. We also believe in aligning our employees' success with the company's long-term growth. As such, in addition to base salary, Neuralink offers equity compensation (in the form of Restricted Stock Units (RSU)) for all full-time employees.
Base Salary Range:
$83,000-$139,000 USD
What We Offer:
Full-time employees are eligible for the following benefits listed below.
  • An opportunity to change the world and work with some of the smartest and most talented experts from different fields
  • Growth potential; we rapidly advance team members who have an outsized impact
  • Excellent medical, dental, and vision insurance through a PPO plan
  • Paid holidays
  • Commuter benefits
  • Meals provided
  • Equity (RSUs) *Temporary Employees & Interns excluded
  • 401(k) plan *Interns initially excluded until they work 1,000 hours
  • Parental leave *Temporary Employees & Interns excluded
  • Flexible time off *Temporary Employees & Interns excluded

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