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Senior Ic Layout Engineer Jobs (NOW HIRING)

SRI International

IC Layout Engineer III

Princeton, NJ · On-site

$92K - $122K/yr

Overview SRI International (formerly Sarnoff Corporation) is looking for a capable IC Layout Engineer in our Princeton, NJ office. The successful candidate will be presented with challenges in IC ...

SRI International

IC Layout Engineer III

Princeton, NJ

$92K - $122K/yr

SRI International (formerly Sarnoff Corporation) is looking for a capable IC Layout Engineer in our Princeton, NJ office. The successful candidate will be presented with challenges in IC Layout and ...

SRI International

IC Layout Engineer III

Princeton, NJ · On-site

$92K - $122K/yr

Overview SRI International (formerly Sarnoff Corporation) is looking for a capable IC Layout Engineer in our Princeton, NJ office. The successful candidate will be presented with challenges in IC ...

Neuralink

Analog IC Layout Engineer

South San Francisco, CA · On-site

$83K - $139K/yr

  • Medical

  • Dental

  • Vision

  • Retirement

As an Analog IC Layout Engineer, your responsibilities will include: * Crafting state-of-the-art layouts for mixed-signal and analog circuits * Amplifiers * Filters * Switched capacitor circuits

Neuralink

Analog IC Layout Engineer

South San Francisco, CA · On-site

$83K - $139K/yr

  • Medical

  • Dental

  • Vision

  • Retirement

As an Analog IC Layout Engineer, your responsibilities will include: * Crafting state-of-the-art layouts for mixed-signal and analog circuits * Amplifiers * Filters * Switched capacitor circuits

Elevate Semiconductor

Staff Analog IC Layout Engineer

San Diego, CA · On-site

$120K - $180K/yr

  • Medical

  • Dental

  • Vision

  • Retirement

  • PTO

... from senior engineers to deliver innovative and cost-effective solutions. Must be able to work ... Minimum of 8 years of professional experience in analog and mixed-signal IC layout design * Strong ...

Elevate Semiconductor

Staff Analog IC Layout Engineer

San Diego, CA · On-site

$120K - $180K/yr

  • Medical

  • Dental

  • Vision

  • Retirement

  • PTO

... from senior engineers to deliver innovative and cost-effective solutions. Must be able to work ... Minimum of 8 years of professional experience in analog and mixed-signal IC layout design * Strong ...

Saige Partners

ANalog Layout Engineer

San Jose, CA · On-site

$236K/yr

Senior High-Speed Mixed-Signal / Analog IC Layout Engineer (San Jose, CA)As an Analog Layout Engineer, you will be responsible for: Layout of Analog / High Speed transceiver circuit blocks such as ...

Skyworks

Sr. Principal IC Layout Designer

Greensboro, NC · On-site

$114K - $220K/yr

  • Medical

  • Retirement

  • PTO

Sr. Principal IC Layout Designer Posting Start Date: 7/10/26 Job Location(s): Greensboro If you are ... Partner with senior analog/RFIC layout engineers to design cellular-band RFICs, including LNAs, RF ...

Skyworks

Sr. Principal IC Layout Designer

Greensboro, NC

$220K/yr

  • Medical

  • Retirement

  • PTO

Sr. Principal IC Layout Designer Posting Start Date: 7/10/26 Job Location(s): Greensboro If you are ... Partner with senior analog/RFIC layout engineers to design cellular-band RFICs, including LNAs, RF ...

Skyworks

Sr. Principal IC Layout Designer

Greensboro, NC · On-site

$114K - $220K/yr

  • Medical

  • Retirement

  • PTO

Sr. Principal IC Layout Designer Posting Start Date: 7/10/26 Job Location(s): Greensboro If you are ... Partner with senior analog/RFIC layout engineers to design cellular-band RFICs, including LNAs, RF ...

IC Enable

Junior IC Layout Design Engineer

Richardson, TX · Hybrid

  • Medical

  • Dental

  • Vision

  • Retirement

Position Overview IC Enable is seeking a motivated and detail-oriented Junior IC Layout Design Engineer to join our growing team in Richardson, Texas. This role is ideal for an early-career engineer ...

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Senior Ic Layout Engineer information

See salary details

$59.5K

$126.6K

$183.5K

How much do senior ic layout engineer jobs pay per year?

As of Aug 16, 2026, the average yearly pay for senior ic layout engineer in the United States is $126,557.00, according to ZipRecruiter salary data. Most workers in this role earn between $104,500.00 and $143,500.00 per year, depending on experience, location, and employer.

What are the key skills and qualifications needed to thrive as a senior IC layout engineer?

To thrive as a Senior IC Layout Engineer, you need expertise in analog and digital IC layout, deep understanding of semiconductor process technologies, and typically a degree in electrical engineering or a related field. Proficiency in layout design tools such as Cadence Virtuoso, familiarity with DRC/LVS verification tools, and knowledge of industry standards are essential. Strong attention to detail, problem-solving skills, and effective communication help ensure collaboration with design and verification teams. These competencies are crucial for creating high-performance, manufacturable integrated circuits that meet rigorous quality and reliability standards.

What is the difference between Senior IC Layout Engineer vs IC Design Engineer?

AspectSenior IC Layout EngineerIC Design Engineer
Primary FocusPhysical layout, placement, routing of integrated circuitsCircuit design, schematic development, functional verification
Skills & CertificationsEDA tools, layout best practices, design rulesCircuit theory, HDL languages, simulation tools
Work EnvironmentFoundries, semiconductor companies, design housesDesign firms, semiconductor companies, R&D labs

While both roles collaborate closely in chip development, the Senior IC Layout Engineer specializes in the physical implementation of circuits, focusing on layout and fabrication constraints. In contrast, the IC Design Engineer concentrates on creating and verifying circuit functionality at the schematic level. Both roles require strong technical skills but differ in their core responsibilities within the chip design process.

What is a senior IC layout engineer?

Senior IC Layout Engineers are specialized professionals who design and implement the physical layout of integrated circuits (ICs) on semiconductor chips. They translate circuit schematics into detailed geometric representations that can be fabricated onto silicon wafers. Their role involves ensuring optimal placement of components, routing of interconnections, and compliance with design rules to achieve desired performance, power, and area targets. Senior engineers typically have advanced experience, oversee complex projects, and may mentor junior team members. They play a critical role in the development of high-performance electronics used in various industries.

What are the main challenges senior IC layout engineers face when working on complex analog or mixed-signal designs?

Senior IC Layout Engineers often encounter challenges related to meeting stringent design specifications, such as minimizing parasitic effects, ensuring signal integrity, and optimizing area usage. Managing multiple iterations with circuit designers and verification teams to address performance and reliability concerns can be demanding, especially under tight project timelines. Additionally, staying updated with evolving EDA tools and process technologies is essential for maintaining productivity and delivering high-quality layouts.

What cities are hiring for Senior Ic Layout Engineer jobs?

Cities with the most Senior Ic Layout Engineer job openings:

What are the most commonly searched types of Ic Layout Engineer jobs?

The most popular types of Ic Layout Engineer jobs are:

What states have the most Senior Ic Layout Engineer jobs?

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Senior Ic Layout Engineer jobs near you
Infographic showing various Senior Ic Layout Engineer job openings in the United States as of August 2026, with employment types broken down into 92% Full Time, 2% Part Time, and 6% Contract. Highlights an 86% Physical, 5% Hybrid, and 9% Remote job distribution, with an average salary of $126,557 per year, or $60.8 per hour.

Analog IC Layout Engineer

Neuralink

South San Francisco, CA

Full-time

Re-posted 19 days ago

Job description

Team Description:

The Brain Interfaces Soc Department delivers chip architecture and silicon implementation of neural recording and stimulation system-on-chip (SoC) for high-bandwidth brain-computer interfaces. We have crafted a team of exceptional engineers whose mission is to push the frontiers of what is possible today and define the future.

Job Description and Responsibilities:

We are looking for experienced and hands-on engineers with a creative and initiative mindset, who are interested in exploring the next-generation chip design with advanced architectures and hardware accelerators with a goal of enhancing the energy efficiency, information entropy, and scalability of our wireless brain-computer interfaces towards the physical limit of silicon technology. The ideal candidates are energetic people who get excited about building things, are highly analytical, and enjoy tackling new problems. You will have the opportunity to collaborate closely with chip designers, electrical engineers, algorithms engineers, and software engineers on a small, agile team. As an Analog IC Layout Engineer, your responsibilities will include:

  • Crafting state-of-the-art layouts for mixed-signal and analog circuits
    • Amplifiers
    • Filters
    • Switched capacitor circuits
    • Oscillators
    • Data converters
    • Power management circuits
  • Reviewing layout floorplans and analyzing high-fidelity circuits with circuit engineers
  • Physical verification of custom IC mask layouts (LVS, DRC, ERC)

Required Qualifications:

  • Bachelor of Science in Computer Engineering or related field
  • 2+ years of experience in analog and mixed-signal IC layout design
  • 1+ year experience with FinFET technologies
  • Ability to identify the best approach to solving problems

Preferred Qualifications:

  • Programming/scripting knowledge in SKILL, TCL, Shell, C/C++, and/or Python
  • Proven expertise in implementing analog and mixed-signal layout designs, achieving tight matching, low noise, and low power consumption
  • Understanding on failure-prone circuit and layout structures
  • Experience with analog DFM standards
  • Experience with layout P-cell design and implementation
  • Experience with layout automation 

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