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Senior Ic Layout Engineer Jobs (NOW HIRING)

Neuralink

Analog IC Layout Engineer

Fremont, CA · On-site

As an Analog IC Layout Engineer, your responsibilities will include: * Crafting state-of-the-art layouts for mixed-signal and analog circuits * Amplifiers * Filters * Switched capacitor circuits

Neuralink

Analog IC Layout Engineer

Fremont, CA · On-site

$83K - $139K/yr

As an Analog IC Layout Engineer, your responsibilities will include: * Crafting state-of-the-art layouts for mixed-signal and analog circuits * Amplifiers * Filters * Switched capacitor circuits

Analog Devices

Lead Analog IC Layout Engineer

Wilmington, MA · On-site

$134K - $201K/yr

Lead Analog IC Layout Engineer About the ATE Group: The Automatic Test Equipment (ATE) organization ... As a Lead Designer, Layout, you hold a senior technical position working on our most complex layout ...

Analog Devices

Principal IC Layout Engineer

Wilmington, MA · On-site

$159K - $239K/yr

Principal IC Layout Engineer About the ATE Group: The Automatic Test Equipment (ATE) organization within Instrumentation delivers high-performance solutions that enable production testing of advanced ...

Glow Networks

Analog Layout Engineer

Santa Clara, CA · On-site

$237K/yr

Senior layout designer, will be responsible for layout of high-performance analog cores such as ... Responsibilities include leading IC layout of cutting-edge high-performance, high-speed CMOS ...

IC Enable

IC Layout Design Engineer

Richardson, TX · Hybrid

The team has an exciting opportunity for a IC Layout Design Engineer V to join our diverse team executing full-custom integrated circuit development with specific responsibility for driving the ...

Falcomm

Senior RFIC Layout Engineer

Atlanta, GA · On-site

$100K - $138K/yr

Falcomm is seeking a Senior RFIC Layout Engineer to support the physical implementation of RF and ... This role focuses on developing high-quality IC layouts for RF front-end circuits while ensuring ...

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How much do senior ic layout engineer jobs pay per year?

As of Jun 7, 2026, the average yearly pay for senior ic layout engineer in the United States is $126,557.00, according to ZipRecruiter salary data. Most workers in this role earn between $104,500.00 and $143,500.00 per year, depending on experience, location, and employer.

What are the key skills and qualifications needed to thrive as a Senior IC Layout Engineer, and why are they important?

To thrive as a Senior IC Layout Engineer, you need expertise in analog and digital IC layout, deep understanding of semiconductor process technologies, and typically a degree in electrical engineering or a related field. Proficiency in layout design tools such as Cadence Virtuoso, familiarity with DRC/LVS verification tools, and knowledge of industry standards are essential. Strong attention to detail, problem-solving skills, and effective communication help ensure collaboration with design and verification teams. These competencies are crucial for creating high-performance, manufacturable integrated circuits that meet rigorous quality and reliability standards.

What is the difference between Senior IC Layout Engineer vs IC Design Engineer?

AspectSenior IC Layout EngineerIC Design Engineer
Primary FocusPhysical layout, placement, routing of integrated circuitsCircuit design, schematic development, functional verification
Skills & CertificationsEDA tools, layout best practices, design rulesCircuit theory, HDL languages, simulation tools
Work EnvironmentFoundries, semiconductor companies, design housesDesign firms, semiconductor companies, R&D labs

While both roles collaborate closely in chip development, the Senior IC Layout Engineer specializes in the physical implementation of circuits, focusing on layout and fabrication constraints. In contrast, the IC Design Engineer concentrates on creating and verifying circuit functionality at the schematic level. Both roles require strong technical skills but differ in their core responsibilities within the chip design process.

What are Senior IC Layout Engineers?

Senior IC Layout Engineers are specialized professionals who design and implement the physical layout of integrated circuits (ICs) on semiconductor chips. They translate circuit schematics into detailed geometric representations that can be fabricated onto silicon wafers. Their role involves ensuring optimal placement of components, routing of interconnections, and compliance with design rules to achieve desired performance, power, and area targets. Senior engineers typically have advanced experience, oversee complex projects, and may mentor junior team members. They play a critical role in the development of high-performance electronics used in various industries.

What are the main challenges Senior IC Layout Engineers face when working on complex analog or mixed-signal designs?

Senior IC Layout Engineers often encounter challenges related to meeting stringent design specifications, such as minimizing parasitic effects, ensuring signal integrity, and optimizing area usage. Managing multiple iterations with circuit designers and verification teams to address performance and reliability concerns can be demanding, especially under tight project timelines. Additionally, staying updated with evolving EDA tools and process technologies is essential for maintaining productivity and delivering high-quality layouts.
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Senior Ic Layout Engineer jobs near you
Sr. Photonic IC Layout Engineer

Sr. Photonic IC Layout Engineer

Skorpios Technologies Inc

Temecula, CA • On-site

$125K - $185K/yr

Full-time

Posted 14 days ago

Job description

Description:

Skorpios is seeking an experienced photonic IC layout engineer to lead the design and layout of chips which will be used in high-performance, high-data rate optical networking products. The successful candidate will join our highly talented engineering team in Albuquerque, NM and report to the Senior Manager of Process Engineering.


  • All tasks related to mask design and layout of photonic integrated circuits
  • Creating mask designs in conjunction with optical designers and process engineers.
  • Creating design rules and implementing within layout software.
  • Leading tape-out process for photonic device designs in conjunction with optical designers and process engineers.
  • Expanding photonic element library within CAD software
  • Organizing and tracking all versions of design layouts.
  • Maintaining database of existing mask sets
Requirements:
  • B.S. (M.S. preferred) in Electrical Engineering, or a closely related field
  • At least five (5) years of work experience in photonic IC layout & design
  • Experience with commercial foundry tape-out process
  • Experience with commercial layout software (Cadence, dw-2000, Mentor Graphics)
  • Deep understanding of DRC rules and their creation.
  • Strong problem solving and critical thinking skills.
  • Strong communication, presentation and documentation skills
  • Must be able to work effectively in a dynamic start-up environment.