Analog Layout Engineer
Santa Clara, CA · On-site
$237K/yr
Role: Analog Layout Engineer Location: Santa Clara, CA (Remote Option available) Duration ... Responsibilities include leading IC layout of cutting-edge high-performance, high-speed CMOS ...
Analog Layout Engineer
Santa Clara, CA · On-site
$237K/yr
Role: Analog Layout Engineer Location: Santa Clara, CA (Remote Option available) Duration ... Responsibilities include leading IC layout of cutting-edge high-performance, high-speed CMOS ...
Analog/RF IC Layout Design Engineer
Santa Clara, CA · On-site
$117K - $195K/yr
Assisting the design team with IC floorplanning, creating grid cells and other custom layouts * Coordinating layout activities with other layout engineers and contractors Complete chip level sign-off ...
Analog/RF IC Layout Design Engineer
Santa Clara, CA · On-site
$117K - $195K/yr
Assisting the design team with IC floorplanning, creating grid cells and other custom layouts * Coordinating layout activities with other layout engineers and contractors Complete chip level sign-off ...
Analog/RF IC Layout Design Engineer
$117K - $195K/yr
Assisting the design team with IC floorplanning, creating grid cells and other custom layouts * Coordinating layout activities with other layout engineers and contractors Complete chip level sign-off ...
Analog/RF IC Layout Design Engineer
$117K - $195K/yr
Assisting the design team with IC floorplanning, creating grid cells and other custom layouts * Coordinating layout activities with other layout engineers and contractors Complete chip level sign-off ...
Analog/RF IC Layout Design Engineer
Colorado Springs, CO · On-site
$117K - $195K/yr
Assisting the design team with IC floorplanning, creating grid cells and other custom layouts * Coordinating layout activities with other layout engineers and contractors Complete chip level sign-off ...
Analog/RF IC Layout Design Engineer
Colorado Springs, CO · On-site
$117K - $195K/yr
Assisting the design team with IC floorplanning, creating grid cells and other custom layouts * Coordinating layout activities with other layout engineers and contractors Complete chip level sign-off ...
Principal Layout * In this role layout engineer with closely work with analog design team to layout and verify custom analog/mixed-signal IPs * Lead full-custom IC layout design and verification ...
Principal Layout * In this role layout engineer with closely work with analog design team to layout and verify custom analog/mixed-signal IPs * Lead full-custom IC layout design and verification ...
Analog Layout Designer
Newport Beach, CA · On-site
$60K - $96K/yr
In this role layout engineer with closely work with analog design team to layout and verify custom analog/mixed-signal IPs * Lead full-custom IC layout design and verification, including chip floor ...
Analog Layout Designer
Newport Beach, CA · On-site
$60K - $96K/yr
In this role layout engineer with closely work with analog design team to layout and verify custom analog/mixed-signal IPs * Lead full-custom IC layout design and verification, including chip floor ...
Layout Engineer
San Jose, CA · On-site +1
$70K - $110K/yr
Familiar & understand CMOS and BiCMOS technology and IC Design principles. * Understanding of CAD ... design engineers and other layout designers. * Work both independently and within a team ...
Layout Engineer
San Jose, CA · On-site +1
$70K - $110K/yr
Familiar & understand CMOS and BiCMOS technology and IC Design principles. * Understanding of CAD ... design engineers and other layout designers. * Work both independently and within a team ...
Senior RFIC Layout Engineer
Atlanta, GA · On-site
$100K - $138K/yr
Falcomm is seeking a Senior RFIC Layout Engineer to support the physical implementation of RF and ... This role focuses on developing high-quality IC layouts for RF front-end circuits while ensuring ...
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Senior RFIC Layout Engineer
Atlanta, GA · On-site
$100K - $138K/yr
Falcomm is seeking a Senior RFIC Layout Engineer to support the physical implementation of RF and ... This role focuses on developing high-quality IC layouts for RF front-end circuits while ensuring ...
Senior RFIC Layout Engineer
Atlanta, GA · On-site
$100K - $138K/yr
Falcomm is seeking a Senior RFIC Layout Engineer to support the physical implementation of RF and ... This role focuses on developing high-quality IC layouts for RF front-end circuits while ensuring ...
Senior RFIC Layout Engineer
Atlanta, GA · On-site
$100K - $138K/yr
Falcomm is seeking a Senior RFIC Layout Engineer to support the physical implementation of RF and ... This role focuses on developing high-quality IC layouts for RF front-end circuits while ensuring ...
Staff Analog Layout Engineer
San Jose, CA · On-site
$180K - $225K/yr
Perform custom IC layout execution of high-speed analog/RF circuits. * Optimize layout solutions to meet stringent TSMC manufacturing constraints, DFM rules, and antenna restrictions * Deliver IP ...
Staff Analog Layout Engineer
San Jose, CA · On-site
$180K - $225K/yr
Perform custom IC layout execution of high-speed analog/RF circuits. * Optimize layout solutions to meet stringent TSMC manufacturing constraints, DFM rules, and antenna restrictions * Deliver IP ...
... IC CAD design files using industry-standard tools, ensuring compliance with design guides, layout ... Generate ECOs (Engineering Change Orders) to release completed drawings and bills of materials ...
... IC CAD design files using industry-standard tools, ensuring compliance with design guides, layout ... Generate ECOs (Engineering Change Orders) to release completed drawings and bills of materials ...
Senior RFIC Layout Engineer
Atlanta, GA · On-site
$100K - $138K/yr
Falcomm is seeking a Senior RFIC Layout Engineer to support the physical implementation of RF and ... This role focuses on developing high-quality IC layouts for RF front-end circuits while ensuring ...
Senior RFIC Layout Engineer
Atlanta, GA · On-site
$100K - $138K/yr
Falcomm is seeking a Senior RFIC Layout Engineer to support the physical implementation of RF and ... This role focuses on developing high-quality IC layouts for RF front-end circuits while ensuring ...
... IC CAD design files using industry-standard tools, ensuring compliance with design guides, layout ... Generate ECOs (Engineering Change Orders) to release completed drawings and bills of materials ...
... IC CAD design files using industry-standard tools, ensuring compliance with design guides, layout ... Generate ECOs (Engineering Change Orders) to release completed drawings and bills of materials ...
... IC CAD design files using industry-standard tools, ensuring compliance with design guides, layout ... Generate ECOs (Engineering Change Orders) to release completed drawings and bills of materials ...
... IC CAD design files using industry-standard tools, ensuring compliance with design guides, layout ... Generate ECOs (Engineering Change Orders) to release completed drawings and bills of materials ...
For over four decades, Cirrus Logic has been propelled by the top engineers in mixed-signal ... Associates Degree in Electronic/IC layout CAD specialization or related program and 10+ years of IC ...
For over four decades, Cirrus Logic has been propelled by the top engineers in mixed-signal ... Associates Degree in Electronic/IC layout CAD specialization or related program and 10+ years of IC ...
Layout Engineer
San Jose, CA · On-site
$70K - $110K/yr
Familiar & understand CMOS and BiCMOS technology and IC Design principles. * Understanding of CAD ... design engineers and other layout designers. * Work both independently and within a team ...
Layout Engineer
San Jose, CA · On-site
$70K - $110K/yr
Familiar & understand CMOS and BiCMOS technology and IC Design principles. * Understanding of CAD ... design engineers and other layout designers. * Work both independently and within a team ...
Responsibilities include leading IC layout of cutting-edge high-performance, high-speed CMOS ... Analog Layout Engineer * Local Skills : Julie Skidmore * Languages Required: : English
Responsibilities include leading IC layout of cutting-edge high-performance, high-speed CMOS ... Analog Layout Engineer * Local Skills : Julie Skidmore * Languages Required: : English
... IC CAD design files using industry-standard tools, ensuring compliance with design guides, layout ... Generate ECOs (Engineering Change Orders) to release completed drawings and bills of materials ...
... IC CAD design files using industry-standard tools, ensuring compliance with design guides, layout ... Generate ECOs (Engineering Change Orders) to release completed drawings and bills of materials ...
... IC CAD design files using industry-standard tools, ensuring compliance with design guides, layout ... Generate ECOs (Engineering Change Orders) to release completed drawings and bills of materials ...
... IC CAD design files using industry-standard tools, ensuring compliance with design guides, layout ... Generate ECOs (Engineering Change Orders) to release completed drawings and bills of materials ...
Understanding of IC layout concepts, verification flow, and post-layout analysis * Knowledgeable in ... Internship or research experience in wireless transceiver or RFIC development * Exposure to Wi-Fi, ...
Understanding of IC layout concepts, verification flow, and post-layout analysis * Knowledgeable in ... Internship or research experience in wireless transceiver or RFIC development * Exposure to Wi-Fi, ...
Internship Ic Layout Engineer information
See salary details
$11.06 - $12.74
2% of jobs
$12.74 - $14.42
4% of jobs
$16.11 is the 25th percentile. Wages below this are outliers.
$14.42 - $16.11
19% of jobs
$16.11 - $17.79
24% of jobs
The median wage is $17.89 / hr.
$17.79 - $19.47
17% of jobs
$20.48 is the 75th percentile. Wages above this are outliers.
$19.47 - $21.15
16% of jobs
$21.15 - $22.84
6% of jobs
$22.84 - $24.52
5% of jobs
$24.52 - $26.20
3% of jobs
$26.20 - $27.88
3% of jobs
$27.88 - $29.57
1% of jobs
$11
$19
$29
How much do internship ic layout engineer jobs pay per hour?
As of Jun 26, 2026, the average hourly pay for internship ic layout engineer in the United States is $19.31, according to ZipRecruiter salary data. Most workers in this role earn between $16.11 and $20.91 per hour, depending on experience, location, and employer.
What is the difference between Internship Ic Layout Engineer vs Internship Digital IC Design Engineer?
| Aspect | Internship Ic Layout Engineer | Internship Digital IC Design Engineer |
|---|---|---|
| Primary Focus | Physical layout and fabrication of integrated circuits | Design and simulation of digital circuit architectures |
| Skills Required | Layout tools, CMOS fabrication, circuit design basics | HDL coding, digital logic, simulation tools |
| Work Environment | Foundries, chip design companies, R&D labs | Semiconductor companies, design firms, R&D labs |
| Common Certifications | None specific, basic electronics knowledge | None specific, digital design fundamentals |
Internship Ic Layout Engineer roles focus on physical design and layout of integrated circuits, working closely with fabrication processes. In contrast, Internship Digital IC Design Engineers concentrate on digital logic design and simulation. Both internships are common in semiconductor industries and require foundational electronics knowledge, but they emphasize different aspects of chip development.
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What states have the most Internship Ic Layout Engineer jobs? States with the most job openings for Internship Ic Layout Engineer jobs include:
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Job description
Role: Analog Layout Engineer
Location: Santa Clara, CA (Remote Option available)
Duration: Long Term
Responsibilities:
Senior layout designer, will be responsible for layout of high-performance analog cores such as analog-to-digital converters, digital-to-analog converters, PLL, transceivers, etc.
Responsibilities include leading IC layout of cutting-edge high-performance, high-speed CMOS integrated circuits in foundry CMOS process nodes in 5nm, 7nm, 16nm, 28nm, 40nm and 65nm following best practices from the industry.
Qualifications
Thorough knowledge of industry standard EDA tools from Cadence, Mentor and Synopsys.
Must be able to set up LVS, DRC, ERC environments and debug verification issues using Cadence and Mentor tools.
Experience with layout of high-performance analog blocks such as analog to digital converters, references, digital to analog converters, PLL etc. desired.
Experience with floor planning, block level routing and top-level chip assembly.
Knowledge of high-performance analog layout techniques such as common centroid layout, shielding, use of dummy devices, thermal aware layout with consideration for electromigration.
Demonstrated experience with analog layout for silicon chips in mass production.
Experience with FinFET process nodes preferred
Experience working with distributed design teams a plus.
Knowledge of skill code and layout automation is a plus.
Self-starter with the ability to define and adhere to a schedule.
Must possess strong written and verbal communication skills.
10+ years' experience in high performance analog layout in advanced CMOS processes.
Location: Santa Clara, CA (Remote Option available)
Duration: Long Term
Responsibilities:
Senior layout designer, will be responsible for layout of high-performance analog cores such as analog-to-digital converters, digital-to-analog converters, PLL, transceivers, etc.
Responsibilities include leading IC layout of cutting-edge high-performance, high-speed CMOS integrated circuits in foundry CMOS process nodes in 5nm, 7nm, 16nm, 28nm, 40nm and 65nm following best practices from the industry.
Qualifications
Thorough knowledge of industry standard EDA tools from Cadence, Mentor and Synopsys.
Must be able to set up LVS, DRC, ERC environments and debug verification issues using Cadence and Mentor tools.
Experience with layout of high-performance analog blocks such as analog to digital converters, references, digital to analog converters, PLL etc. desired.
Experience with floor planning, block level routing and top-level chip assembly.
Knowledge of high-performance analog layout techniques such as common centroid layout, shielding, use of dummy devices, thermal aware layout with consideration for electromigration.
Demonstrated experience with analog layout for silicon chips in mass production.
Experience with FinFET process nodes preferred
Experience working with distributed design teams a plus.
Knowledge of skill code and layout automation is a plus.
Self-starter with the ability to define and adhere to a schedule.
Must possess strong written and verbal communication skills.
10+ years' experience in high performance analog layout in advanced CMOS processes.
About Glow Networks
Sourced by ZipRecruiter
Industry
Telecommunications
Company size
51 - 200 Employees
Headquarters location
Dallas, TX, US
Year founded
2000