Remote Sap Fieldglass Jobs (NOW HIRING)

Description:
Possible 3 Month CTH | No Fees | Do Not Re-Post | Confidential
Skype interview is mandatory please provide the candidates skype ID, VIDEO INTERVIEW IS MANDATORY. NO CPT ALLOWED.
Submit candidates under their legal name and use only Capgemini template
Candidate's photo ID IS MANDATORY FOR ALL CANDIDATES EVEN CITIZENS.
In your submission include:
Phone #:
Email address:
Location (City and State):
Relocate:
Availability to start:
Visa type and expiration date:
Hiring Status: C2C/W2/1099QOpen for CTH (y/n):
Timeslots for Skype interview (provide Skype ID)
Due to additional onboarding requirements, a meet and greet is required for all new hires.
Candidates must be willing to go to the closest Capgemini, Client, or offsite location as indicated by project team to meet with a Capgemini team member prior to starting their assignment.
If the candidate is not local, travel will be required at the expense of the Capgemini project team (will receive project code for vendor to submit invoices in SAP Fieldglass for reimbursement). If travel is involved, will send travel policy document for the candidate to adhere to
Vendors: If your candidate is selected for interview, you need to take screenshot of candidate and interviewer once interview is initiated. THIS IS NOW MANDATORY FOR ALL INTERVIEWS to confirm candidate is same as person in CV.
Marie Samayoa
OBO Tactical Procurement | Procurement
Capgemini North America | Guatemala
Email: Marie.samayoa@capgemini.com
Job Description: SOC Design Verification Engineer
Location: Redmond, WA
Hybrid (Remote option allowed)
Minimum Qualifications
• Track record of 'first-pass success' in ASIC development cycles.
• Bachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience.
• 8 to 10 years of hands-on experience in SystemVerilog/UVM methodology
• Experience in one or more of the following areas along with functional verification-SV Assertions, Formal, Emulation.
• Experience in EDA tools and scripting (Python, TCL, Perl, Shell) used to build tools and flows for verification environments.
Preferred Qualifications
• Experience verifying GPU/CPU designs.
• Experience in development of UVM based verification environments from scratch.
• Experience with Design verification of Data-center applications like Video, AI/ML and Networking designs.
• Experience with revision control systems like Mercurial(Hg), Git or SVN.
• Experience with IP or integration verification of high-speed interfaces like PCIe, DDR, Ethernet.
• Experience working across and building relationships with cross-functional design, model and emulation teams.
• Define and implement SoC verification plans, build verification test benches to enable sub-system/SoC level verification.
• Develop functional tests based on verification test plan.
• Drive Design Verification to closure based on defined verification metrics on test plan, functional and code coverage.
• Debug, root-cause and resolve functional failures in the design, partnering with the Design team.
• Collaborate with cross-functional teams like Design, Model, Emulation and Silicon validation teams towards ensuring the highest design quality.
• Develop and drive continuous Design Verification improvements using the latest verification methodologies, tools and technologies from the industry.
UVM/SV (Priority: 1)
Python/TCL/Perl (Priority: 3)
Synopsys/Cadence EDA Design/Verification tools (Priority: 1)
Named Job Posting? (if Yes - needs to be approved by SCSC)
Additional Details

• Global Grade : C
• Named Job Posting? (if Yes - needs to be approved by SCSC) : No
• Remote work possibility : No
• Global Role Family : 60239 (P) Cloud Infrastructure
• Global Technical Skills Family : 6241 (T) Configuration Management & Versioning Tools
• Local Role Name : SOC Design Verification Engineer
• Local Skills : Julie Skidmore
• Languages Required: : English