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Remote Physical Design Engineer Jobs (NOW HIRING)

K2 Space

Senior ASIC Physical Design Engineer

$170K - $250K/yr

The Role We are seeking a Senior ASIC Physical Design Engineer to help implement advanced SoCs that power next-generation satellite and space systems. In this role, you will contribute to the full ...

Positron AI

ASIC Physical Design Engineer, Principal

$150K - $300K/yr

Required Qualifications * 12+ years of experience in physical design, spanning floorplanning ... Remote-first culture with a company-provided computer and home office setup Compensation and future

Nvidia

Senior CPU Design Engineer

You will work closely with fellow design engineers, architects, verification engineers, and physical design engineers to accomplish your tasks. Whatyouwillbedoing: Drive the micro-architecture ...

Nvidia

Senior CPU Design Engineer

You will work closely with fellow design engineers, architects, verification engineers, and physical design engineers to accomplish your tasks. What you will be doing: * Drive the micro-architecture ...

Nvidia

Senior CPU Design Engineer

OR · On-site +1

You will work closely with fellow design engineers, architects, verification engineers, and physical design engineers to accomplish your tasks. Whatyouwillbedoing: Drive the micro-architecture ...

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Remote Physical Design Engineer information

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$95K

$141.5K

How much do remote physical design engineer jobs pay per year?

As of Sep 5, 2026, the average yearly pay for remote physical design engineer in the United States is $139,408.00, according to ZipRecruiter salary data. Most workers in this role earn between $136,000.00 and $140,000.00 per year, depending on experience, location, and employer.

What is a remote physical design engineer?

A Remote Physical Design Engineer is a professional who specializes in the physical implementation of integrated circuits (ICs) and works from a remote location. Their primary responsibilities include tasks such as floorplanning, placement, routing, and timing closure of semiconductor chips using electronic design automation (EDA) tools. They collaborate with teams across different locations to ensure that the chip layouts meet performance, power, and area requirements. Working remotely, these engineers utilize secure network connections and cloud-based tools to access design environments and communicate with colleagues. This role requires a strong understanding of digital design, VLSI concepts, and proficiency with industry-standard EDA tools.

How do remote physical design engineers typically collaborate with cross-functional teams to ensure design accuracy and project alignment?

Remote Physical Design Engineers work closely with circuit designers, verification engineers, and project managers through virtual meetings, shared project management tools, and version-controlled repositories. Effective communication is crucial, as they frequently review design updates, address integration issues, and ensure that deliverables meet timing, power, and area targets. Collaboration tools like Slack, Zoom, and Jira help bridge the distance, while regular design reviews and milestone check-ins keep everyone aligned. This remote setup encourages proactive communication and documentation to maintain project momentum and design integrity.

What are the key skills and qualifications needed to thrive as a remote physical design engineer, and why are they important?

To thrive as a Remote Physical Design Engineer, you need a solid background in VLSI design, digital circuit fundamentals, and experience with ASIC or FPGA physical implementation, usually supported by a degree in electrical or computer engineering. Expertise in EDA tools like Cadence, Synopsys, or Mentor Graphics, and familiarity with scripting languages such as TCL or Python, are typically required. Strong problem-solving, communication, and time management skills are essential for effective collaboration and project delivery in a remote environment. These competencies ensure efficient design cycles, high-quality silicon, and smooth coordination with distributed teams.

What is the difference between Remote Physical Design Engineer vs Remote ASIC Design Engineer?

AspectRemote Physical Design EngineerRemote ASIC Design Engineer
Required CredentialsBachelor's/Master's in Electrical Engineering or Computer Engineering, knowledge of EDA toolsBachelor's/Master's in Electrical Engineering or Computer Engineering, knowledge of ASIC design tools
Work EnvironmentDesign teams, EDA tool suites, remote collaborationDesign teams, simulation environments, remote collaboration
Industry UsageSemiconductor, electronics manufacturingSemiconductor, electronics manufacturing
Search & Comparison IntentYesYes

The Remote Physical Design Engineer focuses on the physical implementation of integrated circuits, ensuring layout and timing meet specifications. The Remote ASIC Design Engineer is involved earlier in the design process, focusing on architecture and logic design. Both roles require similar educational backgrounds and often work within the same industry sectors, but their responsibilities differ in the design stages they cover.

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Remote Physical Design Engineer jobs near you
Infographic showing various Remote Physical Design Engineer job openings in the United States as of August 2026, with employment types broken down into 72% Full Time, and 28% Contract. Highlights an 100% Remote job distribution, with an average salary of $139,408 per year, or $67 per hour.

Senior ASIC Physical Design Engineer

K2 Space

Remote

$170K - $250K/yr

Full-time

Medical, Dental, Vision, Life, PTO

Re-posted 10 days ago

Job description

K2 is building the largest and highest-power satellites ever flown, unlocking performance levels previously out of reach across every orbit. Backed by over $1 billion in total funding from leading investors including Altimeter Capital, ICONIQ, Kleiner Perkins, Lightspeed Venture Partners, Redpoint Ventures, and T. Rowe Price - and with over $1 billion in signed contracts across commercial and US government customers, we're mass-producing the highest-power satellite platforms ever built for missions from LEO to deep space.
The rise of heavy-lift launch vehicles is shifting the industry from an era of mass constraint to one of mass abundance, and we believe this new era demands a fundamentally different class of spacecraft. Engineered to survive the harshest radiation environments and to fully capitalize on today's and tomorrow's massive rockets, K2 satellites deliver unmatched capability at constellation scale and across multiple orbits.
With multiple launches in 2027 and plans to scale to 100 satellites a year, we're Building Bigger - helping develop the solar system and build toward a Kardashev Type II (K2) civilization. If you are a motivated individual who thrives in a fast-paced environment and you're excited about contributing to the success of a high-growth Series D-funded company, we'd love for you to apply.
The Role
We are seeking a Senior ASIC Physical Design Engineer to help implement advanced SoCs that power next-generation satellite and space systems. In this role, you will contribute to the full physical design flow-from synthesis to GDSII-working closely with architecture, RTL, verification, and packaging teams. You'll be a key contributor in achieving timing closure, optimizing PPA, and supporting design integration with external partners. You will be part of a collaborative design team developing state-of-the-art mixed-signal SoCs to be hosted on some of the largest, most powerful, rapidly designed and rapidly manufactured satellites ever deployed in space. In your first 6 months, you will develop and implement new SoC sub-systems for satellite communications and beyond. In your first two years, you will have contributed to developing cutting-edge SoCs that will fly in space.
Responsibilities
  • Execute the complete physical design flow for complex SoC blocks and top-level integration, including synthesis, floorplanning, place & route, CTS, STA, and physical verification.
  • Perform timing closure and optimization across multiple corners and modes using industry-standard tools.
  • Collaborate with front-end, verification, and DFT teams to ensure clean handoff and predictable convergence.
  • Work with external physical design service providers and internal leads to review deliverables, resolve issues, and ensure schedule alignment.
  • Develop and maintain scripts and automation to improve flow efficiency and consistency.
  • Support physical sign-off activities including DRC/LVS, IR drop, EM, and power analysis.
  • Assist in chip-level integration, ECOs, and tapeout preparation.
  • Contribute to methodology development, tool evaluation, and flow documentation.
  • Support your product through production and spaceflight.

Required Qualifications
  • Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or related field.
  • 5-10 years of experience in ASIC physical design for complex SoCs.
  • Hands-on experience with industry-standard tools (Synopsys ICC2/Fusion Compiler, Cadence Innovus, or equivalent).
  • Strong understanding of timing analysis, power optimization, and physical verification flows.
  • Experience with hierarchical or flat SoC design methodologies.
  • Familiarity with FinFET technologies.
  • Working knowledge of DFT, UPF/CPF power intent, and ECO implementation.
  • Strong problem-solving skills and ability to work cross-functionally in fast-paced environments.

Preferred Qualifications
  • Exposure to radiation-hardened or space-qualified ASICs.
  • Experience with chip-package co-design or advanced packaging (2.5D/3D).
  • Familiarity with physical design service vendor management or offshore collaboration.
  • Experience with sign-off through TSMC.
  • Experience with Gate-All-Around technologies.
  • Experience working in cross-functional, geographically distributed teams.

Compensation and Benefits:
  • Base salary range for this role is $170,000 - $250,000 + equity in the company
  • Salary will be based on several factors including, but not limited to: knowledge and skills, education, and experience level
  • Comprehensive benefits package including paid time off, medical/dental/vision/ coverage, life insurance, paid parental leave, and many other perks

If you don't meet 100% of the preferred skills and experience, we encourage you to still apply! Building a spacecraft unlike any other requires a team unlike any other and non-traditional career twists and turns are encouraged!
If you need a reasonable accommodation as part of your application for employment or interviews with us, please let us know.
Export Compliance
As defined in the ITAR, "U.S. Persons" include U.S. citizens, lawful permanent residents (i.e., Green Card holders), and certain protected individuals (e.g., refugees/asylees, American Samoans). Please consult with a knowledgeable advisor if you are unsure whether you are a "U.S. Person."
The person hired for this role will have access to information and items controlled by U.S. export control regulations, including the export control regulations outlined in the International Traffic in Arms Regulation (ITAR). The person hired for this role must therefore either be a "U.S. person" as defined by 22 C.F.R. § 120.15 or otherwise eligible for a federally issued export control license.
Equal Opportunity
K2 Space is an Equal Opportunity Employer; employment with K2 Space is governed on the basis of merit, competence and qualifications and will not be influenced in any manner by race, color, religion, gender, national origin/ethnicity, veteran status, disability status, age, sexual orientation, gender identity, marital status, mental or physical disability or any other legally protected status.
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About K2 Space

Sourced by ZipRecruiter

Industry

Guided missile and space vehicle manufacturing

Company size

11 - 50 Employees

Headquarters location

Los Angeles, CA, US

Year founded

2022

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