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Pll Jobs (NOW HIRING)

Apple

RFIC - PLL Design Engineer

Irvine, CA

$122K - $214K/yr

As Sr. RFIC - PLL Design Engineer within the Wireless Radio team, you will be at the center of a wireless SoC design group with a critical impact on getting Apple's state-of-the-art wireless ...

Apple

RFIC - PLL Design Engineer

Irvine, CA · On-site

$216K/yr

As Sr. RFIC - PLL Design Engineer within the Wireless Radio team, you will be at the center of a wireless SoC design group with a critical impact on getting Apple's state-of-the-art wireless ...

Apple

RFIC - PLL Design Engineer

Irvine, CA

$122K - $214K/yr

As Sr. RFIC - PLL Design Engineer within the Wireless Radio team, you will be at the center of a wireless SoC design group with a critical impact on getting Apple's state-of-the-art wireless ...

Apple

RFIC - PLL Design Engineer

Irvine, CA

$175K - $308K/yr

As Sr. RFIC - PLL Design Engineer within the Wireless Radio team, you will be at the center of a wireless SoC design group with a critical impact on getting Apple's state-of-the-art wireless ...

Apple

RFIC - PLL Design Engineer

Irvine, CA

$175K - $308K/yr

As Sr. RFIC - PLL Design Engineer within the Wireless Radio team, you will be at the center of a wireless SoC design group with a critical impact on getting Apple's state-of-the-art wireless ...

Apple

RFIC - PLL Design Engineer

Irvine, CA

$122K - $214K/yr

As Sr. RFIC - PLL Design Engineer within the Wireless Radio team, you will be at the center of a wireless SoC design group with a critical impact on getting Apple's state-of-the-art wireless ...

Apple

RFIC - PLL Design Engineer

Irvine, CA

$175K - $308K/yr

As Sr. RFIC - PLL Design Engineer within the Wireless Radio team, you will be at the center of a wireless SoC design group with a critical impact on getting Apple's state-of-the-art wireless ...

Apple

RFIC - PLL Design Engineer

Irvine, CA

$175K - $308K/yr

As Sr. RFIC - PLL Design Engineer within the Wireless Radio team, you will be at the center of a wireless SoC design group with a critical impact on getting Apple's state-of-the-art wireless ...

Apple

RFIC - PLL Design Engineer

Irvine, CA · On-site

$216K/yr

As Sr. RFIC - PLL Design Engineer within the Wireless Radio team, you will be at the center of a wireless SoC design group with a critical impact on getting Apple's state-of-the-art wireless ...

Apple

RFIC - PLL Design Engineer

Irvine, CA

$122K - $214K/yr

As Sr. RFIC - PLL Design Engineer within the Wireless Radio team, you will be at the center of a wireless SoC design group with a critical impact on getting Apple's state-of-the-art wireless ...

Blue Origin

PLL IC Design Engineer - TeraWave

Seattle, WA · On-site +1

$230K - $322K/yr

Extensive experience in the design of PLL building blocks such as VCOs, high-speed integer and frac-N pre-scalers, PFDs, charge-pumps, etc. * Experience with clock domain synchronization techniques ...

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Pll information

See salary details

$10

$23

$43

How much do pll jobs pay per hour?

As of Aug 27, 2026, the average hourly pay for pll in the United States is $23.02, according to ZipRecruiter salary data. Most workers in this role earn between $17.31 and $24.76 per hour, depending on experience, location, and employer.

What is a phase-locked loop?

A Phase-Locked Loop (PLL) is an electronic circuit that synchronizes an output signal's phase and frequency with a reference signal. PLLs are essential in communication systems, radio transmitters, and frequency synthesizers because they help maintain stable and accurate frequencies. They work by continuously comparing the phase of an input signal with that of a controlled oscillator, adjusting the oscillator to match the input. PLLs are widely used in devices like clocks, radios, and wireless communication systems for signal synchronization and noise reduction.

What are the key skills and qualifications needed to thrive as a phase-locked loop engineer?

To excel as a PLL Engineer, you need a solid background in electrical engineering, analog and digital circuit design, and a relevant engineering degree. Familiarity with EDA tools like Cadence, MATLAB for simulation, and experience with semiconductor process technologies are typically required. Strong problem-solving skills, attention to detail, and effective teamwork are crucial soft skills in this role. These qualifications ensure precise design, simulation, and troubleshooting of PLL circuits, which are vital for reliable electronic systems.

What are some common challenges faced by process improvement leaders and how can applicants prepare for them?

Process Improvement Leaders (PILs) often encounter challenges such as resistance to change, aligning cross-functional teams, and quantifying results of implemented improvements. To prepare, applicants should develop strong communication and stakeholder management skills, as well as a solid foundation in data analysis and Lean or Six Sigma methodologies. Demonstrating adaptability and a proactive approach to overcoming obstacles will help you succeed in this dynamic role and contribute to a culture of continuous improvement.

What is the difference between Pll vs Paralegal?

AspectPllParalegal
Required CredentialsLegal education, certification (if applicable)Associate degree or paralegal certificate
Work EnvironmentLaw firms, corporate legal departmentsLaw firms, government agencies, corporations
Industry UsageLegal industry, often specializedLegal support roles across industries
Job ResponsibilitiesLegal research, document preparation, case managementAssisting attorneys, drafting documents, case support

While both Pll and paralegals work in legal environments and support attorneys, Plls often have specialized legal training or certifications, focusing on legal research and case management. Paralegals typically hold formal education like an associate degree and perform a broad range of support tasks. The roles overlap in work environment and responsibilities, but Plls may have more specialized legal knowledge depending on their certification.

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Pll jobs near you
Infographic showing various Pll job openings in the United States as of August 2026, with employment types broken down into 97% Full Time, 1% Part Time, and 2% Contract. Highlights an 88% Physical, 7% Hybrid, and 5% Remote job distribution, with an average salary of $47,881 per year, or $23 per hour.

Principal PLL Design Engineer

Celero Communications, Inc.

Irvine, CA • On-site

$150K - $250K/yr

Full-time

This job post has expired 3 days ago. Applications are no longer accepted.

Job description

Principal PLL Design Engineer
About the job 
Are you a PLL Design Engineer, who is seeking an amazing opportunity delivering disruptive High Speed Interconnect Technology to power next generation AI? We are looking for a High-Speed CMOS PLL Analog Design Engineer –who is excited to join a fast-growing Start-Up Company with a key role for expert in clocking circuits for next generation optical transceivers, high-speed SerDes, and ADC/DAC systems. Candidate will have the opportunity to architect and design PLLs for next generation transceivers.
What You Will Do
• Understand trade-offs between different PLL topologies (e.g., integer-N, fractional-N, all-digital/ADPLL) to meet specifications for power, area, jitter, and frequency range 
• Architect, design and simulate analog/mixed-signal PLL building blocks (VCOs, charge pumps, dividers, PFDs, Loop Filters) at transistor level using tools like Cadence Virtuoso and Spectre 
• Address challenges in advanced node technologies, such as self-heating, electromigration, voltage-controlled oscillator (VCO) linearization and device-level noise optimization 
• Supervise and verify layouts produced by layout engineers to ensure floorplanning, matching, and parasitic minimization using advanced node technologies 
• Be responsible for PLL bring up in the lab, conducting performance characterization using state-of-the-art lab equipment 
• Conduct comprehensive system-level simulations and validation for PLL integration into advanced transceiver technologies 
What You Will Bring
• Master’s degree and/or PhD in Electrical Engineering or related fields with 5+ years of relevant experience in PLL design, and production level tape-out experience. 
• Must have extensive experience with advanced node technologies (16nm/12nm, 7nm, 5nm, 3nm, 2nm processes)  
• Deep understanding of phase noise analysis, VCO design, LDOs and supporting circuitry associated with PLLs 
• Proficient in cadence virtuoso, electromagnetic simulator (e.g., EMX/HFSS), and MATLAB for system-level modelling 
• Strong communication and documentation skills 
Annual Base Salary Range: $150,000 - $250,000 (The final offer will be determined based on job-related skills, experience, qualifications, and location.)