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Remote Analog Layout Jobs (NOW HIRING)

Tenstorrent

Analog Design Engineer

North, SC · On-site +1

$100K - $500K/yr

This role is remote, based out of any in North America . We welcome candidates at various ... A hands-on owner for the full lifecycle: design, verification, layout interaction, tape-out, and ...

Renesas Electronics

Staff Analog Design Engineer

Chandler, AZ · On-site +1

$198K/yr

Lead the design, simulation, verification, and layout supervision of CMOS power management circuits ... Our people-first culture and global support system, including the remote work option and Employee ...

Renesas Electronics

Staff Analog Design Engineer

Chandler, AZ · On-site +1

$198K/yr

Lead the design, simulation, verification, and layout supervision of CMOS power management circuits ... Our people-first culture and global support system, including the remote work option and Employee ...

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How much do remote analog layout jobs pay per hour?

As of Aug 1, 2026, the average hourly pay for remote analog layout in the United States is $21.83, according to ZipRecruiter salary data. Most workers in this role earn between $15.62 and $22.12 per hour, depending on experience, location, and employer.

What is a Remote Analog Layout Engineer?

A Remote Analog Layout Engineer is a professional who specializes in designing the physical layout of analog integrated circuits (ICs), such as amplifiers, data converters, and power management circuits, while working remotely. They use electronic design automation (EDA) tools to create layouts that meet electrical and manufacturing requirements. Their work ensures that the circuit functions as intended and fits within the constraints of the chip design. By working remotely, these engineers collaborate with design teams using online communication tools and are responsible for delivering high-quality layouts on project timelines.

What is the difference between Remote Analog Layout vs Remote Digital Layout?

AspectRemote Analog LayoutRemote Digital Layout
CredentialsEE degree, circuit design knowledgeEE degree, digital circuit understanding
Work EnvironmentDesigning analog circuits, schematic interpretationDesigning digital circuits, FPGA/ASIC layout
Industry UsageSemiconductor, electronics manufacturingSemiconductor, electronics, computing
Search/Comparison IntentUnderstanding analog design rolesUnderstanding digital design roles

Remote Analog Layout involves designing and laying out analog circuits, focusing on continuous signals and precision. Remote Digital Layout centers on digital circuit design, involving logic gates and digital signals. Both roles require similar educational backgrounds but differ in technical focus and application environments.

What are the key skills and qualifications needed to thrive as a Remote Analog Layout Engineer, and why are they important?

To excel as a Remote Analog Layout Engineer, you need a solid background in analog/mixed-signal circuit design, semiconductor physics, and a relevant engineering degree. Expertise with Electronic Design Automation (EDA) tools such as Cadence Virtuoso, and familiarity with design rule checking (DRC) and layout versus schematic (LVS) verification is essential. Attention to detail, problem-solving abilities, and strong communication skills are vital for collaborating with distributed teams and ensuring precision in designs. These competencies are crucial to deliver high-performance, error-free layouts that meet stringent industry standards and project timelines.

What are some common challenges faced by remote analog layout engineers, and how can they be effectively managed?

Remote analog layout engineers often face challenges such as clear communication with design teams, accessing secure design tools, and managing time zone differences. To overcome these obstacles, it’s important to establish regular virtual meetings, use secure remote access solutions for EDA tools, and maintain detailed documentation of design changes. Proactively reaching out to colleagues and leveraging collaborative platforms can also help ensure alignment and smooth workflow despite physical distance.
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Remote Analog Layout jobs near you
Infographic showing various Remote Analog Layout job openings in the United States as of July 2026, with employment types broken down into 100% Full Time. Highlights an 100% Remote job distribution, with an average salary of $45,402 per year, or $21.8 per hour.

High-Speed Analog Layout Design Engineer

Celero Communications, Inc.

San Jose, CA • On-site, Remote

$239K/yr

Full-time

Posted 3 days ago

New

Job description

Senior to Principal High-Speed Analog Layout Design Engineer roles
Locations: Irvine, CA or San Jose, CA or remote
About the Role
Celero Communication Inc. is an exciting and fast-growing start-up in the semiconductor industry, pushing boundaries with innovative technologies that power the world’s most advanced AI and data center infrastructure. As we scale rapidly, we are looking for a driven and resourceful High-Speed Analog Layout Engineer to be the backbone of our daily operations and a key partner in shaping our company culture.
 
We are seeking a Principal/Senior Analog Layout Engineer to drive the layout design of complex analog and mixed-signal IP blocks that are at the heart of our advanced optical communication systems. As a key member of the Analog & Mixed-Signal (AMS) design team, you will lead layout development of critical blocks such as ADCs, DACs, PLLs, and other high-performance analog/mixed-signal circuits. You will interface closely with circuit designers, CAD/PDK teams, and other layout engineers to ensure first-pass silicon success. This is a hands-on technical role ideal for someone who thrives in a fast-paced environment and enjoys mentoring others while contributing directly to cutting-edge chip development.
 
Key Responsibilities
• Lead and own the physical layout design of complex analog/mixed-signal macros (e.g., ADCs, DACs, PLLs), from floor planning through final verification
• Collaborate closely with schematic designers to create optimal layout solutions considering performance, matching, symmetry, and reliability
• Mentor and guide junior layout engineers/contractors across multiple time zones, enforcing best practices in layout design and verification
• Perform and debug full hierarchy LVS, DRC, PERC, ERC, and other signoff checks using industry-standard tools (Pegasus, Calibre, etc.)
• Contribute to chip-level planning including top-level floor planning, block integration, power grid implementation, and signal routing
• Participate in layout design reviews and provide technical leadership for layout quality, verification completeness, and schedule adherence
• Support automation initiatives through scripting and tool customization (SKILL, TCL, Python is a plus)
 
Required Qualifications
• Minimum 10+ years of hands-on analog/mixed-signal layout design experience in advanced CMOS/FinFET technologies
• Proven track record of top level integration IP layout macros and preparing IPs for handoff to Physical Design
• Proven leadership in owning major IP layout macros or full-chip-level layout at FinFET nodes (TSMC preferred)
• At least 1 year of experience with TSMC FinFET process nodes (N3, N5, N7, or N16)
• Deep understanding of device physics, layout-dependent effects (LOD, WPE, OSE, LDE, etc.), and their impact on circuit performance
• Strong expertise in layout best practices for device matching, noise isolation, ESD protection, symmetry, and parasitic minimization
• Proficiency in floor planning, hierarchical block integration, routing strategy, and power/ground grid design
• Expertise with Cadence Virtuoso, Calibre, Pegasus, and other layout and verification tools
• Familiarity with layout verification flows, including LVS, DRC, PERC, Density, DFM, ERC, and Antenna rules
• Experience working in collaborative environments with international and remote teams
• Strong documentation and communication skills with the ability to clearly present layout trade-offs and status to cross-functional teams
• Experience using revision control systems for layout design management
 
Preferred Qualifications
• Exposure to optical or high-speed analog interfaces is a strong plus
• Working knowledge of SKILL, TCL, or Python for layout automation or design flow optimization
• Proven ability to collaborate with international teams (U.S., Canada, Argentina)
• Strong organizational skills with high attention to detail and follow-through
• Ability to multi-task and prioritize in a fast-paced, dynamic environment
• Proactive, eager-to-learn mindset with excellent problem-solving skills
 
What We Offer
• The chance to play a foundational role at a high-growth semiconductor start-up
• Exposure to a wide variety of cross functional teams
• A collaborative, international team culture where ideas and initiative are valued
• The opportunity to grow alongside Celero as we scale and shape the future of our industry
• A foundational role at a fast-growing semiconductor start-up shaping the future of AI and data center connectivity
 
Note: Since we have several roles available, candidate job level will be evaluated during interview process.