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Remote Analog Layout Jobs (NOW HIRING)

Analog Design Engineer

North, SC · On-site +1

$100K - $500K/yr

This role is remote, based out of any in North America . We welcome candidates at various ... A hands-on owner for the full lifecycle: design, verification, layout interaction, tape-out, and ...

Staff Analog Design Engineer

Chandler, AZ · On-site +1

$198K/yr

Lead the design, simulation, verification, and layout supervision of CMOS power management circuits ... Our people-first culture and global support system, including the remote work option and Employee ...

Staff Analog Design Engineer

Chandler, AZ · On-site +1

$198K/yr

Lead the design, simulation, verification, and layout supervision of CMOS power management circuits ... Our people-first culture and global support system, including the remote work option and Employee ...

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Remote Analog Layout information

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How much do remote analog layout jobs pay per hour?

As of Aug 21, 2026, the average hourly pay for remote analog layout in the United States is $21.83, according to ZipRecruiter salary data. Most workers in this role earn between $15.62 and $22.12 per hour, depending on experience, location, and employer.

What is a remote analog layout engineer?

A Remote Analog Layout Engineer is a professional who specializes in designing the physical layout of analog integrated circuits (ICs), such as amplifiers, data converters, and power management circuits, while working remotely. They use electronic design automation (EDA) tools to create layouts that meet electrical and manufacturing requirements. Their work ensures that the circuit functions as intended and fits within the constraints of the chip design. By working remotely, these engineers collaborate with design teams using online communication tools and are responsible for delivering high-quality layouts on project timelines.

What are the key skills and qualifications needed to thrive as a remote analog layout engineer, and why are they important?

To excel as a Remote Analog Layout Engineer, you need a solid background in analog/mixed-signal circuit design, semiconductor physics, and a relevant engineering degree. Expertise with Electronic Design Automation (EDA) tools such as Cadence Virtuoso, and familiarity with design rule checking (DRC) and layout versus schematic (LVS) verification is essential. Attention to detail, problem-solving abilities, and strong communication skills are vital for collaborating with distributed teams and ensuring precision in designs. These competencies are crucial to deliver high-performance, error-free layouts that meet stringent industry standards and project timelines.

What are some common challenges faced by remote analog layout engineers, and how can they be effectively managed?

Remote analog layout engineers often face challenges such as clear communication with design teams, accessing secure design tools, and managing time zone differences. To overcome these obstacles, it’s important to establish regular virtual meetings, use secure remote access solutions for EDA tools, and maintain detailed documentation of design changes. Proactively reaching out to colleagues and leveraging collaborative platforms can also help ensure alignment and smooth workflow despite physical distance.

What is the difference between Remote Analog Layout vs Remote Digital Layout?

AspectRemote Analog LayoutRemote Digital Layout
CredentialsEE degree, circuit design knowledgeEE degree, digital circuit understanding
Work EnvironmentDesigning analog circuits, schematic interpretationDesigning digital circuits, FPGA/ASIC layout
Industry UsageSemiconductor, electronics manufacturingSemiconductor, electronics, computing
Search/Comparison IntentUnderstanding analog design rolesUnderstanding digital design roles

Remote Analog Layout involves designing and laying out analog circuits, focusing on continuous signals and precision. Remote Digital Layout centers on digital circuit design, involving logic gates and digital signals. Both roles require similar educational backgrounds but differ in technical focus and application environments.

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Infographic showing various Remote Analog Layout job openings in the United States as of August 2026, with employment types broken down into 81% Full Time, 14% Part Time, 2% Contract, and 3% Nights. Highlights an 94% Physical, 2% Hybrid, and 4% Remote job distribution, with an average salary of $45,402 per year, or $21.8 per hour.

Senior High Speed Mixed-Signal I/O & Analog Layout Engineer

Saige Partners

San Jose, CA • On-site, Remote

$100 - $110/hr

Full-time

Re-posted 20 days ago


Job description

Job Description We strive to be Your Future, Your Solution to accelerate your career. Contact Christine Gonzalez at cgonzalez@saigpartners.com, you can also schedule an appointment, to learn more about this opportunity. Senior High-Speed Mixed-Signal / Analog IC Layout Engineer Position Summary We are seeking an experienced Senior High-Speed Mixed-Signal / Analog IC Layout Engineer to join our advanced silicon design team

In this role, you will collaborate closely with circuit designers based in San Jose, California, to develop and implement high-performance custom layouts for next-generation mixed-signal integrated circuits. You will be responsible for the physical layout of complex analog and high-speed circuits, including high-speed SERDES receivers (RX), transmitters (TX), PLLs, CDRs, voltage-controlled oscillators (VCOs), analog reference circuits, and other critical building blocks. This position requires a strong understanding of advanced CMOS technologies, layout optimization techniques, and industry-standard EDA tools to ensure designs meet performance, area, reliability, and manufacturability requirements.

Key Responsibilities Partner with remote circuit designers to develop chip floorplans and optimize layouts for performance, area, parasitics, and manufacturability. Create custom analog and mixed-signal layouts for high-speed SERDES and related circuitry using Cadence Virtuoso. Optimize layouts to minimize parasitic effects while maximizing circuit performance and silicon efficiency.

Develop project schedules, estimate layout effort, and execute work to meet aggressive development timelines. Interpret foundry process documentation and implement solutions to address design rule requirements, latch-up prevention, reliability concerns, and manufacturability. Perform layout verification and deliver DRC- and LVS-clean designs using industry-standard verification tools.

Collaborate with cross-functional engineering teams to resolve design, verification, and implementation challenges. Contribute to chip-level physical design activities, including bump planning, pad ring development, ESD implementation, and tape-out preparation. Clearly communicate technical issues, layout trade-offs, and project status through meetings, documentation, and written communication.

Required Qualifications Bachelor's degree in Electrical Engineering, Computer Engineering, or a related discipline with 5+ years of professional IC layout experience; OR 8+ years of professional integrated circuit layout experience in lieu of a degree. Strong experience with custom analog and mixed-signal IC layout. Proficiency with Cadence Virtuoso and physical verification tools including Calibre LVS and DRC.

Experience working with advanced sub-micron CMOS technologies. Strong understanding of layout matching techniques, parasitic optimization, reliability considerations, and design rule compliance. Excellent communication skills with the ability to collaborate effectively across geographically distributed engineering teams.

Self-motivated with the ability to work independently while managing multiple priorities. Preferred Qualifications Extensive experience designing high-speed SERDES layouts, including TX, RX, PLL, CDR, VCO, clocking circuits, and analog reference blocks. Experience with advanced semiconductor process nodes, including FinFET (14nm, 8nm, 4nm) and Gate-All-Around (2nm) technologies.

Experience designing layouts supporting data rates up to 224 Gb/s. Working knowledge of Linux development environments. Experience with Cadence SKILL or SkillCAD automation.

Familiarity with chip-level physical design including bump planning, pad ring implementation, and ESD strategies. Experience leading small layout teams and supporting successful analog or mixed-signal IC tape-outs. Strong technical documentation and written communication skills.

What Success Looks Like The ideal candidate combines deep technical expertise in custom analog layout with strong collaboration skills and attention to detail. You are passionate about solving complex physical design challenges, thrive in a fast-paced engineering environment, and consistently deliver high-quality layouts that meet aggressive performance and schedule goals. Saige Partners, one of the fastest growing technology and talent companies in the Midwest, believes in people with a passion to help them succeed.

We are in the business of helping professionals Build Careers, Not Jobs. Saige Partners believes employees are the most valuable asset to building a thriving and successful company culture. Contact us to learn more about the opportunity below or check out other opportunities at https://careers.saigepartners.com/.