Design circuit components (e.g., DAC, SAR-ADC, S/H, Analog Front-End, PLL, reference generation, clock distribution) required to implement the architecture in advanced FinFET process PREFERRED ...
Design circuit components (e.g., DAC, SAR-ADC, S/H, Analog Front-End, PLL, reference generation, clock distribution) required to implement the architecture in advanced FinFET process PREFERRED ...
Design circuit components (e.g., DAC, SAR-ADC, S/H, Analog Front-End, PLL, reference generation, clock distribution) required to implement the architecture in advanced FinFET process PREFERRED ...
Design circuit components (e.g., DAC, SAR-ADC, S/H, Analog Front-End, PLL, reference generation, clock distribution) required to implement the architecture in advanced FinFET process PREFERRED ...
High speed analog circuit design, such as high-speed broadband amplifiers (VGA, CTLE, DRV, etc.) Clock generation and distribution (VCOs, PLL, clock distribution, etc.) Fundamental analog blocks ...
High speed analog circuit design, such as high-speed broadband amplifiers (VGA, CTLE, DRV, etc.) Clock generation and distribution (VCOs, PLL, clock distribution, etc.) Fundamental analog blocks ...
Set up and validate peripheral device interfaces for DAC, ADC, DDS, PLL, digital potentiometers, and RF attenuator/amplifier ICs communicating over SPI and LVDS, following interface specifications ...
Set up and validate peripheral device interfaces for DAC, ADC, DDS, PLL, digital potentiometers, and RF attenuator/amplifier ICs communicating over SPI and LVDS, following interface specifications ...
Set up and validate peripheral device interfaces for DAC, ADC, DDS, PLL, digital potentiometers, and RF attenuator/amplifier ICs communicating over SPI and LVDS, following interface specifications ...
Quick apply
Set up and validate peripheral device interfaces for DAC, ADC, DDS, PLL, digital potentiometers, and RF attenuator/amplifier ICs communicating over SPI and LVDS, following interface specifications ...
Implement and test high-speed peripheral control for DAC, ADC, DDS, PLL, digital potentiometers, and RF attenuator/amplifier ICs communicating over SPI and LVDS * Design and implement digital control ...
Implement and test high-speed peripheral control for DAC, ADC, DDS, PLL, digital potentiometers, and RF attenuator/amplifier ICs communicating over SPI and LVDS * Design and implement digital control ...
Implement and test high-speed peripheral control for DAC, ADC, DDS, PLL, digital potentiometers, and RF attenuator/amplifier ICs communicating over SPI and LVDS * Design and implement digital control ...
Quick apply
Implement and test high-speed peripheral control for DAC, ADC, DDS, PLL, digital potentiometers, and RF attenuator/amplifier ICs communicating over SPI and LVDS * Design and implement digital control ...
Our team is developing industry-leading mixed-signal Digital PLL Application specific integrated circuits. You can be a part of a growing mixed design and verification team giving you a chance to ...
Our team is developing industry-leading mixed-signal Digital PLL Application specific integrated circuits. You can be a part of a growing mixed design and verification team giving you a chance to ...
Principal SerDes System/DSP Design Engineer
Ottawa, ON · On-site
CA$126K - CA$201K/yr
Provide system level specifications for different sub-blocks of SerDes transceivers such as DAC, ADC, AFE, PLL. * Evaluate and model IMDD optical links and formulate strategies to enhance system ...
Principal SerDes System/DSP Design Engineer
Ottawa, ON · On-site
CA$126K - CA$201K/yr
Provide system level specifications for different sub-blocks of SerDes transceivers such as DAC, ADC, AFE, PLL. * Evaluate and model IMDD optical links and formulate strategies to enhance system ...
Examples of layout designed by our team include Phase Locked Loop (PLL), Delay Locked Loop (DLL), Voltage Controlled Oscillator (VCO), Digital to Analog Converter (DAC), Current Regulator, High Speed ...
Examples of layout designed by our team include Phase Locked Loop (PLL), Delay Locked Loop (DLL), Voltage Controlled Oscillator (VCO), Digital to Analog Converter (DAC), Current Regulator, High Speed ...
Contribute to DFT planning and implementation of technologies such as scan compression, memory built-in self-test (MBIST), logic built-in self-test (LBIST), PLL-based at-speed testing, and on-chip ...
Contribute to DFT planning and implementation of technologies such as scan compression, memory built-in self-test (MBIST), logic built-in self-test (LBIST), PLL-based at-speed testing, and on-chip ...
Contribute to DFT planning and implementation of technologies such as scan compression, memory built-in self-test (MBIST), logic built-in self-test (LBIST), PLL-based at-speed testing, and on-chip ...
Contribute to DFT planning and implementation of technologies such as scan compression, memory built-in self-test (MBIST), logic built-in self-test (LBIST), PLL-based at-speed testing, and on-chip ...
Contribute to DFT planning and implementation of technologies such as scan compression, memory built-in self-test (MBIST), logic built-in self-test (LBIST), PLL-based at-speed testing, and on-chip ...
Contribute to DFT planning and implementation of technologies such as scan compression, memory built-in self-test (MBIST), logic built-in self-test (LBIST), PLL-based at-speed testing, and on-chip ...
Principal Engineer - Analog Design
Ottawa, ON · On-site
CA$107K - CA$157K/yr
These circuits include multi-GHz PLL circuits, high speed digital circuits, MEMS drivers and high-speed performance IO pads. As an Analog Design Engineer and a member of the Analog IP team, you will:
Principal Engineer - Analog Design
Ottawa, ON · On-site
CA$107K - CA$157K/yr
These circuits include multi-GHz PLL circuits, high speed digital circuits, MEMS drivers and high-speed performance IO pads. As an Analog Design Engineer and a member of the Analog IP team, you will:
Contribute to DFT planning and implementation of technologies such as scan compression, memory built-in self-test (MBIST), logic built-in self-test (LBIST), PLL-based at-speed testing, and on-chip ...
Contribute to DFT planning and implementation of technologies such as scan compression, memory built-in self-test (MBIST), logic built-in self-test (LBIST), PLL-based at-speed testing, and on-chip ...
Principal Engineer - Analog Design
Ottawa, ON · On-site
CA$107K - CA$157K/yr
These circuits include multi-GHz PLL circuits, high speed digital circuits, MEMS drivers and high-speed performance IO pads. As an Analog Design Engineer and a member of the Analog IP team, you will:
Principal Engineer - Analog Design
Ottawa, ON · On-site
CA$107K - CA$157K/yr
These circuits include multi-GHz PLL circuits, high speed digital circuits, MEMS drivers and high-speed performance IO pads. As an Analog Design Engineer and a member of the Analog IP team, you will:
Examples of layout designed by our team include Phase- Locked Loop (PLL), Delay -Locked Loop (DLL), Voltage Controlled Oscillator (VCO), Digital to Analog Converter (DAC), Current Regulator, High ...
Examples of layout designed by our team include Phase- Locked Loop (PLL), Delay -Locked Loop (DLL), Voltage Controlled Oscillator (VCO), Digital to Analog Converter (DAC), Current Regulator, High ...
Senior Analog Layout Engineer
CA$114K - CA$182K/yr
ADC, DAC, PLL, SERDES ...) * Proficiency in using industry-standard layout tools (e.g., Cadence Virtuoso, Siemens Calibre, Ansys Totem ...) and familiarity with layout design flows for advanced ...
Senior Analog Layout Engineer
CA$114K - CA$182K/yr
ADC, DAC, PLL, SERDES ...) * Proficiency in using industry-standard layout tools (e.g., Cadence Virtuoso, Siemens Calibre, Ansys Totem ...) and familiarity with layout design flows for advanced ...
ADC, DAC, PLL, SERDES ...) * Proficiency in using industry-standard layout tools (e.g., Cadence Virtuoso, Siemens Calibre, Ansys Totem ...) and familiarity with layout design flows for advanced ...
ADC, DAC, PLL, SERDES ...) * Proficiency in using industry-standard layout tools (e.g., Cadence Virtuoso, Siemens Calibre, Ansys Totem ...) and familiarity with layout design flows for advanced ...
Senior Analog Design Engineer
Ottawa, ON · On-site
CA$114K - CA$182K/yr
... PLL circuits, transimpedance amplifiers, modulator driver circuits, and critical precision analog circuits for control and monitoring functions, etc. In this role: * You will be responsible to ...
Senior Analog Design Engineer
Ottawa, ON · On-site
CA$114K - CA$182K/yr
... PLL circuits, transimpedance amplifiers, modulator driver circuits, and critical precision analog circuits for control and monitoring functions, etc. In this role: * You will be responsible to ...
Pll information
See Ontario salary details
$22.01 is the 25th percentile. Wages below this are outliers.
$17.07 - $23.80
34% of jobs
$23.80 - $30.53
0% of jobs
$30.53 - $37.26
0% of jobs
$37.26 - $43.99
0% of jobs
$43.99 - $50.72
0% of jobs
$50.72 - $57.45
15% of jobs
The median wage is $57.73 / hr.
$57.45 - $64.18
12% of jobs
$69.90 is the 75th percentile. Wages above this are outliers.
$64.18 - $70.91
15% of jobs
$70.91 - $77.64
9% of jobs
$77.64 - $84.37
5% of jobs
$84.37 - $91.11
8% of jobs
$17
$51
$91
How much do pll jobs pay per hour?
As of Aug 27, 2026, the average hourly pay for pll in Ontario is $51.46, according to ZipRecruiter salary data. Most workers in this role earn between $20.67 and $69.71 per hour, depending on experience, location, and employer.
What is a phase-locked loop?
A Phase-Locked Loop (PLL) is an electronic circuit that synchronizes an output signal's phase and frequency with a reference signal. PLLs are essential in communication systems, radio transmitters, and frequency synthesizers because they help maintain stable and accurate frequencies. They work by continuously comparing the phase of an input signal with that of a controlled oscillator, adjusting the oscillator to match the input. PLLs are widely used in devices like clocks, radios, and wireless communication systems for signal synchronization and noise reduction.
What are the key skills and qualifications needed to thrive as a phase-locked loop engineer?
To excel as a PLL Engineer, you need a solid background in electrical engineering, analog and digital circuit design, and a relevant engineering degree. Familiarity with EDA tools like Cadence, MATLAB for simulation, and experience with semiconductor process technologies are typically required. Strong problem-solving skills, attention to detail, and effective teamwork are crucial soft skills in this role. These qualifications ensure precise design, simulation, and troubleshooting of PLL circuits, which are vital for reliable electronic systems.
What are some common challenges faced by process improvement leaders and how can applicants prepare for them?
Process Improvement Leaders (PILs) often encounter challenges such as resistance to change, aligning cross-functional teams, and quantifying results of implemented improvements. To prepare, applicants should develop strong communication and stakeholder management skills, as well as a solid foundation in data analysis and Lean or Six Sigma methodologies. Demonstrating adaptability and a proactive approach to overcoming obstacles will help you succeed in this dynamic role and contribute to a culture of continuous improvement.
What is the difference between Pll vs Paralegal?
| Aspect | Pll | Paralegal |
|---|---|---|
| Required Credentials | Legal education, certification (if applicable) | Associate degree or paralegal certificate |
| Work Environment | Law firms, corporate legal departments | Law firms, government agencies, corporations |
| Industry Usage | Legal industry, often specialized | Legal support roles across industries |
| Job Responsibilities | Legal research, document preparation, case management | Assisting attorneys, drafting documents, case support |
While both Pll and paralegals work in legal environments and support attorneys, Plls often have specialized legal training or certifications, focusing on legal research and case management. Paralegals typically hold formal education like an associate degree and perform a broad range of support tasks. The roles overlap in work environment and responsibilities, but Plls may have more specialized legal knowledge depending on their certification.
What are popular job titles related to Pll jobs in Ontario?
For Pll jobs in Ontario, the most frequently searched job titles are:
What job categories do people searching Pll jobs in Ontario look for?
The top searched job categories for Pll jobs in Ontario are:
Analog/Mixed-Signal SerDes Design Engineer
Markham, ON • Hybrid
Amd •
Computer and Electronic Product Manufacturing • 5 - 10K employees5,001 - 10,000 employees
8.6
Based on 13 frontline employees who took The Breakroom Quiz
27th of 159 rated electronics manufacturers
People enjoy working here
Good employer
Respectful managers
Learn new skills
Uninterrupted breaks
Full-time
Re-posted 18 days ago
Job description
WHAT YOU DO AT AMD CHANGES EVERYTHING
At AMD, our mission is to build great products that accelerate next-generation computing experiences-from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you'll discover the real differentiator is our culture. We push the limits of innovation to solve the world's most important challenges-striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career.
ResponsibilitiesTHE ROLE:
The candidate will be responsible for the design of high-speed ADC-based receivers, DAC-based transmitters, or silicon photonics transceivers. AMD Serdes Technology Group develops high-performance, multi-protocol wireline transceivers in state-of-the-art CMOS process. We are currently seeking an analog/mixed-signal design intern to join our world-class team.
THE PERSON:
A motivated and detailoriented individual who communicates clearly, collaborates well with others, and approaches complex design challenges with curiosity and a strong problemsolving mindset. They are eager to learn, receptive to feedback, and able to work effectively in a fastpaced, researchdriven environment.KEY RESPONSIBILITIES:
- Define circuit architectures optimized for high bandwidth electrical and optical links
- Perform link level simulation in Matlab and/or SPICE to prove the architecture
- Perform design and modeling of on-die RF passive components (e.g., inductors and capacitors) and/or optical structures
- Design circuit components (e.g., DAC, SAR-ADC, S/H, Analog Front-End, PLL, reference generation, clock distribution) required to implement the architecture in advanced FinFET process
PREFERRED EXPERIENCE:
- Experience in design & simulation of analog/mixed signal circuits (ADC, DAC, CTLE, PLL, Clocking circuits..etc) for SerDes links
- Hands on experiences in CMOS circuit designs with advanced technology nodes
- Proficient in CAD Tools for simulations and design implementation
- Experience design of wireline and optical transceiver building blocks
- Good communication skills
- Strong circuit design experiences in high-speed SerDes
- A penchant for problem solving
ACADEMIC CREDENTIALS:
- BS or MS or PhD in Electrical Engineering
LOCATION: Markham, Vancouver, Ottawa
#LI-TB2
#LI-HYBRID
QualificationsBenefits offered are described: AMD benefits at a glance.
AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants' needs under the respective laws throughout all stages of the recruitment and selection process.
AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD's "Responsible AI Policy" is available here.
This posting is for an existing vacancy.
Employment Type: FULL_TIME
About Advanced Micro Devices (AMD)
Sourced by ZipRecruiter
Industry
Computer and electronic product manufacturing and manufacturing
Company size
5,001 - 10,000 Employees
Headquarters location
Sunnyvale, CA, US
Website
What Advanced Micro Devices employees say
Pay
Benefits
Hours and flexibility
Workplace
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