PLL Design Engineer
$200K/yr
Demonstrated proficiency in PLL/FLL and frequency synthesis architecture and circuit design. This includes digital and analog approaches, DCO/VCO design both RO and LC, Fractional-N, SSC, Spur and ...
PLL Design Engineer
$200K/yr
Demonstrated proficiency in PLL/FLL and frequency synthesis architecture and circuit design. This includes digital and analog approaches, DCO/VCO design both RO and LC, Fractional-N, SSC, Spur and ...
PLL Design Engineer
Austin, TX · On-site
$200K/yr
Demonstrated proficiency in PLL/FLL and frequency synthesis architecture and circuit design. This includes digital and analog approaches, DCO/VCO design both RO and LC, Fractional-N, SSC, Spur and ...
PLL Design Engineer
Austin, TX · On-site
$200K/yr
Demonstrated proficiency in PLL/FLL and frequency synthesis architecture and circuit design. This includes digital and analog approaches, DCO/VCO design both RO and LC, Fractional-N, SSC, Spur and ...
PLL Design Engineer
Austin, TX · On-site
$200K/yr
Demonstrated proficiency in PLL/FLL and frequency synthesis architecture and circuit design. This includes digital and analog approaches, DCO/VCO design both RO and LC, Fractional-N, SSC, Spur and ...
PLL Design Engineer
Austin, TX · On-site
$200K/yr
Demonstrated proficiency in PLL/FLL and frequency synthesis architecture and circuit design. This includes digital and analog approaches, DCO/VCO design both RO and LC, Fractional-N, SSC, Spur and ...
PLL Design Engineer
$200K/yr
Demonstrated proficiency in PLL/FLL and frequency synthesis architecture and circuit design. This includes digital and analog approaches, DCO/VCO design both RO and LC, Fractional-N, SSC, Spur and ...
PLL Design Engineer
$200K/yr
Demonstrated proficiency in PLL/FLL and frequency synthesis architecture and circuit design. This includes digital and analog approaches, DCO/VCO design both RO and LC, Fractional-N, SSC, Spur and ...
RF Applications Engineer
Dallas, TX · On-site
Staff Product Applications Engineer - PLL/VCO & Phased Array Radar About the Role As a Staff Product Applications Engineer at Analog Devices (ADI), you will serve as a technical authority for PLL ...
RF Applications Engineer
Dallas, TX · On-site
Staff Product Applications Engineer - PLL/VCO & Phased Array Radar About the Role As a Staff Product Applications Engineer at Analog Devices (ADI), you will serve as a technical authority for PLL ...
RF Applications Engineer
Dallas, TX · On-site
$140 - $190/hr
Senior Product Applications Engineer - PLL/VCO & Phased Array Radar About the Role: As a Senior Product Applications Engineer at Analog Devices (ADI), you will serve as a technical authority for PLL ...
RF Applications Engineer
Dallas, TX · On-site
$140 - $190/hr
Senior Product Applications Engineer - PLL/VCO & Phased Array Radar About the Role: As a Senior Product Applications Engineer at Analog Devices (ADI), you will serve as a technical authority for PLL ...
RF Applications Engineer
Dallas, TX · On-site
Senior Product Applications Engineer - PLL/VCO & Phased Array Radar About the Role As a Senior Product Applications Engineer at Analog Devices (ADI), you will serve as a technical authority for PLL ...
RF Applications Engineer
Dallas, TX · On-site
Senior Product Applications Engineer - PLL/VCO & Phased Array Radar About the Role As a Senior Product Applications Engineer at Analog Devices (ADI), you will serve as a technical authority for PLL ...
Deep experience in RF PLL design including Sigma delta, FRAC-N PLL. Phase noise and spurius signal, settling time. Experience with PLL buildng blocks such as PFD, charge pumps, dividers, multipliers.
Deep experience in RF PLL design including Sigma delta, FRAC-N PLL. Phase noise and spurius signal, settling time. Experience with PLL buildng blocks such as PFD, charge pumps, dividers, multipliers.
Deep experience in RF PLL design including Sigma delta, FRAC-N PLL. Phase noise and spurius signal, settling time. Experience with PLL buildng blocks such as PFD, charge pumps, dividers, multipliers.
Deep experience in RF PLL design including Sigma delta, FRAC-N PLL. Phase noise and spurius signal, settling time. Experience with PLL buildng blocks such as PFD, charge pumps, dividers, multipliers.
Analog Design Engineer
Austin, TX · On-site
$200K/yr
Such as PLL's, DAC, ADC's, SerDes, high-speed timing circuits, Phase-Interpolators etc.., including Top-level / system understanding of such complex blocks * Design, Development, and Verification of ...
Analog Design Engineer
Austin, TX · On-site
$200K/yr
Such as PLL's, DAC, ADC's, SerDes, high-speed timing circuits, Phase-Interpolators etc.., including Top-level / system understanding of such complex blocks * Design, Development, and Verification of ...
Principal Analog Design Engineer - Mixed-Signal PHY (Clocking / High-Speed I/O)
Richardson, TX · On-site
$183K/yr
Lead the development of specialized analog components, focusing primarily on clocking (PLL, DLL, CDR) and transmitter/receiver circuits. * Contribute to the top-level PHY analog architecture ...
Principal Analog Design Engineer - Mixed-Signal PHY (Clocking / High-Speed I/O)
Richardson, TX · On-site
$183K/yr
Lead the development of specialized analog components, focusing primarily on clocking (PLL, DLL, CDR) and transmitter/receiver circuits. * Contribute to the top-level PHY analog architecture ...
DLL/PLL-based clocking solutions for multi-GHz operation * Voltage, reference generation, and power-aware IO design * Drive closure on timing, jitter, noise, SI/PI, and PVT robustness for aggressive ...
DLL/PLL-based clocking solutions for multi-GHz operation * Voltage, reference generation, and power-aware IO design * Drive closure on timing, jitter, noise, SI/PI, and PVT robustness for aggressive ...
DSP Algorithm Engineer
Austin, TX · On-site
$141K - $165K/yr
... PLL/VCO) and specifications • Experience with analog circuit calibrations Educational Background : BSc in Electrical Engineering
DSP Algorithm Engineer
Austin, TX · On-site
$141K - $165K/yr
... PLL/VCO) and specifications • Experience with analog circuit calibrations Educational Background : BSc in Electrical Engineering
DLL/PLL-based clocking solutions for multi-GHz operation * Voltage, reference generation, and power-aware IO design * Drive closure on timing, jitter, noise, SI/PI, and PVT robustness for aggressive ...
DLL/PLL-based clocking solutions for multi-GHz operation * Voltage, reference generation, and power-aware IO design * Drive closure on timing, jitter, noise, SI/PI, and PVT robustness for aggressive ...
Physical Design Engineer, PnR
Austin, TX · On-site
$100K - $500K/yr
I3C, UART), signoff breadth (DRC/LVS, EM/IR, LEC/Formality), multi-clock/CDC-aware implementation, PLL/DLL integration, and DFT-aware physical implementation (OCC/MBIST). What we need * Execute ...
Physical Design Engineer, PnR
Austin, TX · On-site
$100K - $500K/yr
I3C, UART), signoff breadth (DRC/LVS, EM/IR, LEC/Formality), multi-clock/CDC-aware implementation, PLL/DLL integration, and DFT-aware physical implementation (OCC/MBIST). What we need * Execute ...
DLL/PLL-based clocking solutions for multi-GHz operation * Voltage, reference generation, and power-aware IO design * Drive closure on timing, jitter, noise, SI/PI, and PVT robustness for aggressive ...
DLL/PLL-based clocking solutions for multi-GHz operation * Voltage, reference generation, and power-aware IO design * Drive closure on timing, jitter, noise, SI/PI, and PVT robustness for aggressive ...
DLL/PLL-based clocking solutions for multi-GHz operation * Voltage, reference generation, and power-aware IO design * Drive closure on timing, jitter, noise, SI/PI, and PVT robustness for aggressive ...
DLL/PLL-based clocking solutions for multi-GHz operation * Voltage, reference generation, and power-aware IO design * Drive closure on timing, jitter, noise, SI/PI, and PVT robustness for aggressive ...
DLL/PLL-based clocking solutions for multi-GHz operation * Voltage, reference generation, and power-aware IO design * Drive closure on timing, jitter, noise, SI/PI, and PVT robustness for aggressive ...
DLL/PLL-based clocking solutions for multi-GHz operation * Voltage, reference generation, and power-aware IO design * Drive closure on timing, jitter, noise, SI/PI, and PVT robustness for aggressive ...
Principal Analog Design Engineer - Mixed-Signal PHY (Clocking / High-Speed I/O)
Richardson, TX · On-site
$183K/yr
Lead the development of specialized analog components, focusing primarily on clocking (PLL, DLL, CDR) and transmitter/receiver circuits. * Contribute to the top-level PHY analog architecture ...
Principal Analog Design Engineer - Mixed-Signal PHY (Clocking / High-Speed I/O)
Richardson, TX · On-site
$183K/yr
Lead the development of specialized analog components, focusing primarily on clocking (PLL, DLL, CDR) and transmitter/receiver circuits. * Contribute to the top-level PHY analog architecture ...
DLL/PLL-based clocking solutions for multi-GHz operation * Voltage, reference generation, and power-aware IO design * Drive closure on timing, jitter, noise, SI/PI, and PVT robustness for aggressive ...
DLL/PLL-based clocking solutions for multi-GHz operation * Voltage, reference generation, and power-aware IO design * Drive closure on timing, jitter, noise, SI/PI, and PVT robustness for aggressive ...
Pll information
See Texas salary details
$9.63 - $12.46
3% of jobs
$12.46 - $15.29
9% of jobs
$16.18 is the 25th percentile. Wages below this are outliers.
$15.29 - $18.12
42% of jobs
$18.12 - $20.95
20% of jobs
$21.25 is the 75th percentile. Wages above this are outliers.
$20.95 - $23.78
8% of jobs
$23.78 - $26.61
4% of jobs
$26.61 - $29.44
1% of jobs
$29.44 - $32.27
1% of jobs
$32.27 - $35.10
6% of jobs
$35.10 - $37.93
3% of jobs
$37.93 - $40.76
2% of jobs
$9
$21
$40
How much do pll jobs pay per hour?
As of Aug 27, 2026, the average hourly pay for pll in Texas is $21.45, according to ZipRecruiter salary data. Most workers in this role earn between $16.11 and $23.08 per hour, depending on experience, location, and employer.
What is a phase-locked loop?
A Phase-Locked Loop (PLL) is an electronic circuit that synchronizes an output signal's phase and frequency with a reference signal. PLLs are essential in communication systems, radio transmitters, and frequency synthesizers because they help maintain stable and accurate frequencies. They work by continuously comparing the phase of an input signal with that of a controlled oscillator, adjusting the oscillator to match the input. PLLs are widely used in devices like clocks, radios, and wireless communication systems for signal synchronization and noise reduction.
What are the key skills and qualifications needed to thrive as a phase-locked loop engineer?
To excel as a PLL Engineer, you need a solid background in electrical engineering, analog and digital circuit design, and a relevant engineering degree. Familiarity with EDA tools like Cadence, MATLAB for simulation, and experience with semiconductor process technologies are typically required. Strong problem-solving skills, attention to detail, and effective teamwork are crucial soft skills in this role. These qualifications ensure precise design, simulation, and troubleshooting of PLL circuits, which are vital for reliable electronic systems.
What are some common challenges faced by process improvement leaders and how can applicants prepare for them?
Process Improvement Leaders (PILs) often encounter challenges such as resistance to change, aligning cross-functional teams, and quantifying results of implemented improvements. To prepare, applicants should develop strong communication and stakeholder management skills, as well as a solid foundation in data analysis and Lean or Six Sigma methodologies. Demonstrating adaptability and a proactive approach to overcoming obstacles will help you succeed in this dynamic role and contribute to a culture of continuous improvement.
What is the difference between Pll vs Paralegal?
| Aspect | Pll | Paralegal |
|---|---|---|
| Required Credentials | Legal education, certification (if applicable) | Associate degree or paralegal certificate |
| Work Environment | Law firms, corporate legal departments | Law firms, government agencies, corporations |
| Industry Usage | Legal industry, often specialized | Legal support roles across industries |
| Job Responsibilities | Legal research, document preparation, case management | Assisting attorneys, drafting documents, case support |
While both Pll and paralegals work in legal environments and support attorneys, Plls often have specialized legal training or certifications, focusing on legal research and case management. Paralegals typically hold formal education like an associate degree and perform a broad range of support tasks. The roles overlap in work environment and responsibilities, but Plls may have more specialized legal knowledge depending on their certification.
What are popular job titles related to Pll jobs in Texas?
For Pll jobs in Texas, the most frequently searched job titles are:
What job categories do people searching Pll jobs in Texas look for?
The top searched job categories for Pll jobs in Texas are:
PLL Design Engineer
Austin, TX
Apple •
Computer and Electronic Product Manufacturing • 10K+ employees10,000+ employees
8.1
Based on 678 frontline employees who took The Breakroom Quiz
7th of 30 rated technology retailers
People enjoy working here
Good employer
Recommended by students
Paid breaks
Recommended by parents
$200K/yr
Full-time
Re-posted 17 days ago
Job description
At Apple, our products are revolutionizing the way people live across the globe. Within our Analog-Mixed/Signal group, your role will be crucial in pushing the boundaries of what our technology can achieve. We are dedicated to crafting high-quality, innovative hard IPs that surpass the ordinary, adjusting to the escalating complexity of SOC/PHY designs and multiplying projects within tight production schedules. Our environment thrives on these challenges, fueled by a team of exceptional individuals passionate about continual learning and making a substantial impact. If you excel in dynamic settings, relish collaborative problem-solving, and seek to make a societal impact through your work, you might be the ideal candidate for our team. At Apple, you'll join a culture that encourages you to take ownership of your career, supported by colleagues committed to making a difference.
Description
In this role, you will leverage your expertise to develop cutting-edge frequency synthesizers for a variety of applications, including Compute, SoC, SerDes, and Cellular technologies. Your work will directly contribute to maintaining Apple’s leadership in innovation and market presence, setting new standards in the tech industry.
Preferred Qualifications
Technical Expertise: Demonstrated proficiency in PLL/FLL and frequency synthesis architecture and circuit design. This includes digital and analog approaches, DCO/VCO design both RO and LC, Fractional-N, SSC, Spur and Jitter cancellation techniques ..etc
Good knowledge of band gaps, bias circuits, op-amps, LDOs, feedback and compensation techniques.
Clocking Mastery: Deep understanding of clocking fundamentals, with a solid grasp of phase noise, jitter analysis, budgeting, and feedback loop dynamics.
Simulation and Modeling: Skilled in developing System Verilog models, and performing behavioral simulations to explore new architectural performance and impact on loop dynamics. Ability to design/debug RTL is a plus.
Attention to Detail: Exceptional focus on understanding the problems at hand and their systemic impacts, ensuring thoroughness in problem-solving.
Innovation and Learning: A history of innovation and self-directed learning, with demonstrated leadership skills and a growth mindset.
Team Collaboration: Outstanding teamwork capabilities paired with strong productivity and scripting skills, ideally with experience in using industry-standard design tools.
Minimum Qualifications
BSEE with at least 10 years of relevant experience
Description
In this role, you will leverage your expertise to develop cutting-edge frequency synthesizers for a variety of applications, including Compute, SoC, SerDes, and Cellular technologies. Your work will directly contribute to maintaining Apple’s leadership in innovation and market presence, setting new standards in the tech industry.
Preferred Qualifications
Technical Expertise: Demonstrated proficiency in PLL/FLL and frequency synthesis architecture and circuit design. This includes digital and analog approaches, DCO/VCO design both RO and LC, Fractional-N, SSC, Spur and Jitter cancellation techniques ..etc
Good knowledge of band gaps, bias circuits, op-amps, LDOs, feedback and compensation techniques.
Clocking Mastery: Deep understanding of clocking fundamentals, with a solid grasp of phase noise, jitter analysis, budgeting, and feedback loop dynamics.
Simulation and Modeling: Skilled in developing System Verilog models, and performing behavioral simulations to explore new architectural performance and impact on loop dynamics. Ability to design/debug RTL is a plus.
Attention to Detail: Exceptional focus on understanding the problems at hand and their systemic impacts, ensuring thoroughness in problem-solving.
Innovation and Learning: A history of innovation and self-directed learning, with demonstrated leadership skills and a growth mindset.
Team Collaboration: Outstanding teamwork capabilities paired with strong productivity and scripting skills, ideally with experience in using industry-standard design tools.
Minimum Qualifications
BSEE with at least 10 years of relevant experience
About Apple
Sourced by ZipRecruiter
Imagine what you could do here! At Apple, new ideas have a way of becoming extraordinary products, services, and customer experiences very quickly. Bring passion and dedication to your job and there's no telling what you could accomplish. Dynamic, intelligent people and inspiring, innovative technologies are the norm here. The people who work here have reinvented entire industries with all Apple Hardware products. The same real passion for innovation that goes into our products also applies to our practices strengthening our dedication to leave the world better than we found it.
Industry
Computer and electronic product manufacturing
Company size
10,000+ Employees
Headquarters location
Cupertino, CA, US
Year founded
1976
