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Locum Asic Rtl Design Engineer Jobs in Texas (NOW HIRING)

Qualcomm

GPU Design Engineer

Austin, TX · On-site

Provide hands-on technical leadership across RTL design and design verification, including ... Extensive experience delivering complex GPU, CPU, and/or ASIC designs from micro-architecture ...

Cornelis Networks

PCIe ASIC Design Engineer

Austin, TX · On-site +1

Debug functional and performance issues at RTL, gate-level, and silicon. * Ensure compliance with ... Engineering, or related field. * 10+ years of industry experience in ASIC/SoC design with a focus ...

Infotech Sourcing

Design Engineer III

Austin, TX · On-site

Job Title: Core Engineering - Design Engineer III Duration: 12 months with possible extension ... Minimum Qualifications Demonstrated experience with RTL-to-GDSII design flow usage and development ...

Intel

Senior CPU RTL Design Engineer

Austin, TX · On-site

As a CPU RTL Logic Design Engineer your responsibilities will include but are not limited to: Collaborates, drives and develops logic design, register transfer level (RTL) coding, and simulation for ...

Meta

ASIC Engineer, Architecture

Austin, TX

$178K/yr

As an ASIC Engineer specializing in performance and modeling, you will define and drive the ... Collaborate with architecture, RTL design, and physical design teams to translate performance ...

Infotech Sourcing

Design Engineer III

Austin, TX · On-site

Job Title: Core Engineering - Design Engineer III Duration: 12 months with possible extension ... Minimum Qualifications Demonstrated experience with RTL-to-GDSII design flow usage and development ...

Cisco

Senior ASIC Physical Design Engineer

Austin, TX

$165K - $241K/yr

Your Impact As a Physical Design Engineer, you will play a key role in the full RTL-to-GDSII ... Own and drive RTL-to-GDSII implementation for advanced nodes (sub-16nm to 3nm). * Define and ...

Cornelis Networks

PCIe ASIC Design Engineer

Austin, TX · On-site

Debug functional and performance issues at RTL, gate-level, and silicon. * Ensure compliance with ... Engineering, or related field. * 10+ years of industry experience in ASIC/SoC design with a focus ...

Apple

FE RTL Infrastructure - CAD Engineer

Austin, TX · On-site

$164K/yr

Description As a Front-End (FE) RTL Infrastructure - CAD Engineer, you will play a major role in developing and supporting a reliable infrastructure and work environments that design and verification ...

H R PUNDITS INC

Design Engineer III

Austin, TX · On-site

$120K/yr

Design Engineer III ONSITE- US: TX- Austin OR Sunnyvale office (2nd option) Salary 140 to 145K ... Minimum Qualifications Demonstrated experience with RTL-to-GDSII design flow usage and development ...

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Locum Asic Rtl Design Engineer information

What is the difference between Locum Asic Rtl Design Engineer vs Contract Asic Rtl Design Engineer?

AspectLocum Asic Rtl Design EngineerContract Asic Rtl Design Engineer
CredentialsTypically requires relevant engineering degrees and RTL design experienceSimilar credentials, often with specific RTL design certifications
Work EnvironmentTemporary, short-term assignments often in multiple locationsProject-based roles, usually in a fixed location or remote
Employer UsageUsed by agencies or companies needing immediate, short-term expertiseEngaged by companies or staffing agencies for project-specific work

Both roles involve RTL design skills for ASIC development, but a Locum Asic Rtl Design Engineer typically fills short-term, temporary positions, often through staffing agencies, while a Contract Asic Rtl Design Engineer is engaged for specific projects with defined durations. The main difference lies in the nature and duration of employment, but both require similar technical credentials and work environments.

What are the most commonly searched types of Asic Rtl Design Engineer jobs in Texas? The most popular types of Asic Rtl Design Engineer jobs in Texas are:
What are popular job titles related to Locum Asic Rtl Design Engineer jobs in Texas? For Locum Asic Rtl Design Engineer jobs in Texas, the most frequently searched job titles are:
What job categories do people searching Locum Asic Rtl Design Engineer jobs in Texas look for? The top searched job categories for Locum Asic Rtl Design Engineer jobs in Texas are:
What cities in Texas are hiring for Locum Asic Rtl Design Engineer jobs? Cities in Texas with the most Locum Asic Rtl Design Engineer job openings:
Locum Asic Rtl Design Engineer jobs near you
Infographic showing various Locum Asic Rtl Design Engineer job openings in Texas as of July 2026, with employment types broken down into 92% Full Time, 3% Part Time, 2% Contract, 1% Nights, and 2% Summer. Highlights an 89% Physical, 6% Hybrid, and 5% Remote job distribution.
System IP/RTL Design Engineer_Austin, TX (Onsite)_only xoriant W2

System IP/RTL Design Engineer_Austin, TX (Onsite)_only xoriant W2

Xoriant Corporation

Austin, TX • On-site

$90/hr

Other

Re-posted 17 days ago

Job description

Xoriant is an equal opportunity employer. No person shall be excluded from consideration for employment because of race, ethnicity, religion, caste, gender, gender identity, sexual orientation, marital status, national origin, age, disability or veteran status.

TITLE:- System IP/RTL Design Engineer

LOCATION Austin, TX (Onsite)

DURATION 6+ Months (May get extend)

MODE OF INTERVIEW Onsite

RATE $90 per hour on W2

JOB DESCRIPTION

Key responsibilities include:

  • Work on RTL design of System IP blocks
  • Work independently while closely collaborating with other designers as well as members of verification, physical design, performance and power teams
  • Work on developing and maintaining Front-End Tools, Flows and Methodologies
  • Work on creating scripts that automate repetitive daily tasks of team members Support Silicon bring-up activities

Minimum requirements:

  • Proficient in RTL design using Verilog and System Verilog
  • Experienced in setting up and maintaining front-end tools for Synthesis, LEC, Lint and Low Power Analysis
  • Excellent debug and problem-solving skills. Experienced in Silicon bring-up activities
  • Experienced in timing and coverage closure
  • Proficient with UNIX/Linux and programming languages such as PERL, Python, TCL, and Unix Shell Scripting
  • Prior experience of having worked with interconnects, caches and/or cache coherency would be an added advantage

Preferred candidate will possess the following:

  • Verilog/System Verilog
  • GIT
  • Perl
  • Python
  • Tcl/Tk
  • C/C++
  • Jenkins, Jira

Apply