Senior FPGA Engineer
Dayton, OH · Hybrid
$116K - $153K/yr
... Transfer Level (RTL) architecture. * IP Development: Design, implement, and test custom ... Strong programming skills in C, C++, and scripting languages like Python or Tcl for automation.
Dayton, OH · Hybrid
$116K - $153K/yr
... Transfer Level (RTL) architecture. * IP Development: Design, implement, and test custom ... Strong programming skills in C, C++, and scripting languages like Python or Tcl for automation.
Dayton, OH · Hybrid
$116K - $153K/yr
... Transfer Level (RTL) architecture. * IP Development: Design, implement, and test custom ... Strong programming skills in C, C++, and scripting languages like Python or Tcl for automation.
SERMA Group's Productivity Engineering division is seeking an experienced Director of Operations in Germany to lead and optimize our operational performance across ASIC design execution ...
SERMA Group's Productivity Engineering division is seeking an experienced Director of Operations in Germany to lead and optimize our operational performance across ASIC design execution ...
Dayton, OH · On-site
$116K - $153K/yr
... Transfer Level (RTL) architecture. * IP Development: Design, implement, and test custom ... Strong programming skills in C, C++, and scripting languages like Python or Tcl for automation.
Dayton, OH · On-site
$116K - $153K/yr
... Transfer Level (RTL) architecture. * IP Development: Design, implement, and test custom ... Strong programming skills in C, C++, and scripting languages like Python or Tcl for automation.
Dayton, OH · On-site
$116K - $153K/yr
The engineer is responsible for implementing complex digital signal processing (DSP) algorithms ... Transfer Level (RTL) architecture. * IP Development: Design, implement, and test custom ...
Quick apply
Dayton, OH · On-site
$116K - $153K/yr
The engineer is responsible for implementing complex digital signal processing (DSP) algorithms ... Transfer Level (RTL) architecture. * IP Development: Design, implement, and test custom ...
$99K - $225K/yr
... engineer with a background in Field Programmable Gate Array (FPGA) design, you will help solve ... Experience with EDA tools for HDL and RTL simulation, such as ModelSim, Questa, Xcelium, VCS, or ...
$99K - $225K/yr
... engineer with a background in Field Programmable Gate Array (FPGA) design, you will help solve ... Experience with EDA tools for HDL and RTL simulation, such as ModelSim, Questa, Xcelium, VCS, or ...
Massillon, OH · On-site
$54 - $70.25/hr
Apart from designing industry-leading ASIC chips and manufacturing mining rigs, the Group handles ... Design and build distributed systems for cluster management, scheduling, and resource allocation
Massillon, OH · On-site
$54 - $70.25/hr
Apart from designing industry-leading ASIC chips and manufacturing mining rigs, the Group handles ... Design and build distributed systems for cluster management, scheduling, and resource allocation
Massillon, OH · On-site
$54 - $70.25/hr
Apart from designing industry-leading ASIC chips and manufacturing mining rigs, the Group handles ... Design and build distributed systems for cluster management, scheduling, and resource allocation
Quick apply
Massillon, OH · On-site
$54 - $70.25/hr
Apart from designing industry-leading ASIC chips and manufacturing mining rigs, the Group handles ... Design and build distributed systems for cluster management, scheduling, and resource allocation
Wright-patterson Air Force Base, OH
$99K - $225K/yr
... engineer with a background in Field Programmable Gate Array (FPGA) design, you will help solve ... Experience with EDA tools for HDL and RTL simulation, such as ModelSim, Questa, Xcelium, VCS, or ...
Wright-patterson Air Force Base, OH
$99K - $225K/yr
... engineer with a background in Field Programmable Gate Array (FPGA) design, you will help solve ... Experience with EDA tools for HDL and RTL simulation, such as ModelSim, Questa, Xcelium, VCS, or ...
Beavercreek, OH · On-site
$99K - $225K/yr
... engineer with a background in Field Programmable Gate Array (FPGA) design, you will help solve ... Experience with EDA tools for HDL and RTL simulation, such as ModelSim, Questa, Xcelium, VCS, or ...
Beavercreek, OH · On-site
$99K - $225K/yr
... engineer with a background in Field Programmable Gate Array (FPGA) design, you will help solve ... Experience with EDA tools for HDL and RTL simulation, such as ModelSim, Questa, Xcelium, VCS, or ...
Beavercreek, OH · On-site
$99K - $225K/yr
... engineer with a background in Field Programmable Gate Array (FPGA) design, you will help solve ... Experience with EDA tools for HDL and RTL simulation, such as ModelSim, Questa, Xcelium, VCS, or ...
Beavercreek, OH · On-site
$99K - $225K/yr
... engineer with a background in Field Programmable Gate Array (FPGA) design, you will help solve ... Experience with EDA tools for HDL and RTL simulation, such as ModelSim, Questa, Xcelium, VCS, or ...
Drive design decisions and establish engineering standards (code quality, testing strategy, CI/CD ... TypeScript; modern React patterns; UI testing (Jest/RTL/Cypress). * Python frameworks (FastAPI ...
Drive design decisions and establish engineering standards (code quality, testing strategy, CI/CD ... TypeScript; modern React patterns; UI testing (Jest/RTL/Cypress). * Python frameworks (FastAPI ...
Columbus, OH · On-site
$123K - $175K/yr
Drive design decisions and establish engineering standards (code quality, testing strategy, CI/CD ... TypeScript; modern React patterns; UI testing (Jest/RTL/Cypress). * Python frameworks (FastAPI ...
Columbus, OH · On-site
$123K - $175K/yr
Drive design decisions and establish engineering standards (code quality, testing strategy, CI/CD ... TypeScript; modern React patterns; UI testing (Jest/RTL/Cypress). * Python frameworks (FastAPI ...
Drive design decisions and establish engineering standards (code quality, testing strategy, CI/CD ... TypeScript; modern React patterns; UI testing (Jest/RTL/Cypress). * Python frameworks (FastAPI ...
Drive design decisions and establish engineering standards (code quality, testing strategy, CI/CD ... TypeScript; modern React patterns; UI testing (Jest/RTL/Cypress). * Python frameworks (FastAPI ...
... design decisions and establish engineering standards (code quality, testing strategy, CI/CD ... Preferred : • TypeScript; modern React patterns; UI testing (Jest/RTL/Cypress). • Python ...
... design decisions and establish engineering standards (code quality, testing strategy, CI/CD ... Preferred : • TypeScript; modern React patterns; UI testing (Jest/RTL/Cypress). • Python ...
Columbus, OH · On-site
$119K - $157K/yr
We conduct research and development, manage national laboratories, design and manufacture products ... ASIC and FPGA). Our projects are non-standard, highly customized, and will push you to new levels ...
Columbus, OH · On-site
$119K - $157K/yr
We conduct research and development, manage national laboratories, design and manufacture products ... ASIC and FPGA). Our projects are non-standard, highly customized, and will push you to new levels ...
Alpha, OH · On-site
$99K - $225K/yr
... engineer with a background in Field Programmable Gate Array (FPGA) design, you will help solve ... Experience with EDA tools for HDL and RTL simulation, such as ModelSim, Questa, Xcelium, VCS, or ...
Alpha, OH · On-site
$99K - $225K/yr
... engineer with a background in Field Programmable Gate Array (FPGA) design, you will help solve ... Experience with EDA tools for HDL and RTL simulation, such as ModelSim, Questa, Xcelium, VCS, or ...
Columbus, OH · On-site
$119K - $157K/yr
We conduct research and development, manage national laboratories, design and manufacture products ... ASIC and FPGA). Our projects are non-standard, highly customized, and will push you to new levels ...
Columbus, OH · On-site
$119K - $157K/yr
We conduct research and development, manage national laboratories, design and manufacture products ... ASIC and FPGA). Our projects are non-standard, highly customized, and will push you to new levels ...
Digital, analog, microprocessor, ASIC PCB design, EMI (Immunity and Emissions), Magnetics ... Real-time programming in Embedded C * Experience with Stage Gate project management * Experienced ...
Digital, analog, microprocessor, ASIC PCB design, EMI (Immunity and Emissions), Magnetics ... Real-time programming in Embedded C * Experience with Stage Gate project management * Experienced ...
$98K - $134K/yr
Review engineering design documents for anti-tamper solutions (e.g. Anti-Tamper Plans) and conduct ... Working knowledge of modern electronic components, to include microprocessors, FPGAs, and ASIC ...
$98K - $134K/yr
Review engineering design documents for anti-tamper solutions (e.g. Anti-Tamper Plans) and conduct ... Working knowledge of modern electronic components, to include microprocessors, FPGAs, and ASIC ...
$98K - $134K/yr
Review engineering design documents for anti-tamper solutions (e.g. Anti-Tamper Plans) and conduct ... Working knowledge of modern electronic components, to include microprocessors, FPGAs, and ASIC ...
$98K - $134K/yr
Review engineering design documents for anti-tamper solutions (e.g. Anti-Tamper Plans) and conduct ... Working knowledge of modern electronic components, to include microprocessors, FPGAs, and ASIC ...
| Aspect | Locum Asic Rtl Design Engineer | Contract Asic Rtl Design Engineer |
|---|---|---|
| Credentials | Typically requires relevant engineering degrees and RTL design experience | Similar credentials, often with specific RTL design certifications |
| Work Environment | Temporary, short-term assignments often in multiple locations | Project-based roles, usually in a fixed location or remote |
| Employer Usage | Used by agencies or companies needing immediate, short-term expertise | Engaged by companies or staffing agencies for project-specific work |
Both roles involve RTL design skills for ASIC development, but a Locum Asic Rtl Design Engineer typically fills short-term, temporary positions, often through staffing agencies, while a Contract Asic Rtl Design Engineer is engaged for specific projects with defined durations. The main difference lies in the nature and duration of employment, but both require similar technical credentials and work environments.
$116K - $153K/yr
Full-time
Medical, Dental, Vision, Life, Retirement, PTO
Re-posted 2 days ago
Tangram Flex is seeking a Senior FPGA Engineer with a Software/Firmware Focus to design, develop, and optimize high-performance digital logic circuits. This role bridges the gap between hardware architecture and software, and is responsible for implementing complex digital signal processing (DSP) algorithms, managing high-speed data protocols, and ensuring seamless integration with host software systems.
JOB RESPONSIBILITIES/
DESIRED SKILLS & EXPERIENCE/
Required Skills:
Desired Skills:
What We Do: At Tangram, our people and products empower innovators to design, develop, verify, and advance critical systems that strengthen our nation's security. By accelerating the delivery of mission-critical software capabilities, Tangram is transforming how our nation solves its most complex software challenges.
We are committed to staying rooted in our core value of Team First. For that reason, we've designed a highly competitive benefits program and supportive work environment to engage employees and their families.
Tangram Flex is an Equal Opportunity Employer, and provides reasonable accommodation for qualified individuals with disabilities and disabled veterans in its application procedures and in accordance with federal law. All qualified candidates will receive consideration for employment based on business needs, job requirements, and individual qualifications.
EEO/AA Vet/Disabled Employer/ and E-Verify
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Guided missile and space vehicle manufacturing
51 - 200 Employees
Dayton, OH, US
2018