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Junior Rtl Design Engineer Jobs in Ohio (NOW HIRING)

Crane Design Engineer

Springfield, OH · On-site +1

$125K - $175K/yr

Lead Design Engineer / Crane Design Engineer / Structural Design Engineer - Overhead Cranes ... Mentor and guide junior engineers while remaining hands-on About You * Bachelor's degree in ...

Mid-level Design Engineer

Miamisburg, OH · On-site

$85K - $140K/yr

Mentor and assist junior engineers in developing final design and constructions plans. * Coordinate design activities and meetings between design staff, subcontractors and client managers.

Mid-level Design Engineer

Independence, OH · On-site

$85K - $140K/yr

Mentor and assist junior engineers in developing final design and constructions plans. * Coordinate design activities and meetings between design staff, subcontractors and client managers.

Roadway Design Engineer

Miamisburg, OH · On-site

$90K - $125K/yr

Mentor and assist junior engineers in developing final design plans (including but not limited to implementation and knowledge of cross sections, traffic control, drainage, and signing and pavement ...

Roadway Design Engineer

Independence, OH · On-site

$90K - $125K/yr

Mentor and assist junior engineers in developing final design plans (including but not limited to implementation and knowledge of cross sections, traffic control, drainage, and signing and pavement ...

Mentor junior RF engineers and guide Engineering Technicians to complete project tasks effectively. * Collaborate with CAD engineers to capture design details accurately. * Write test plans, reports ...

Mentor and coach junior and mid-level engineers, promoting best practices in design, documentation, and problem solving. Core Competencies * Strong analytical and problem solving skills * Hands on ...

Mechanical Design Engineer

Beaver, OH · On-site

$66.20K - $89.70K/yr

Direct the work of technical support staff and mentor junior engineers in mechanical and fluid-system design; guide troubleshooting and modifications to resolve equipment malfunctions * Perform ...

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Mechanical Design Engineer

Wellston, OH · On-site

$59.50K - $80.70K/yr

Direct the work of technical support staff and mentor junior engineers in mechanical and fluid-system design; guide troubleshooting and modifications to resolve equipment malfunctions * Perform ...

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Mechanical Design Engineer

Bourneville, OH · On-site

$68.30K - $92.60K/yr

Direct the work of technical support staff and mentor junior engineers in mechanical and fluid-system design; guide troubleshooting and modifications to resolve equipment malfunctions * Perform ...

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Showing results 1-20

Junior Rtl Design Engineer information

See Ohio salary details

$31.8K

$68.3K

$104.1K

How much do junior rtl design engineer jobs pay per year?

As of May 28, 2026, the average yearly pay for junior rtl design engineer in Ohio is $68,259.00, according to ZipRecruiter salary data. Most workers in this role earn between $46,100.00 and $76,100.00 per year, depending on experience, location, and employer.

What are the key skills and qualifications needed to thrive as a Junior RTL Design Engineer, and why are they important?

To thrive as a Junior RTL Design Engineer, a solid background in digital logic design, hardware description languages (such as Verilog or VHDL), and a relevant engineering degree are essential. Experience with simulation and synthesis tools (like ModelSim, Synopsys, or Xilinx Vivado) and a basic understanding of ASIC or FPGA flows are typically required. Strong analytical thinking, attention to detail, and effective teamwork skills help individuals excel in translating specifications into efficient hardware designs. These skills ensure accurate, reliable, and high-performance digital circuit development, which is crucial for meeting project goals and industry standards.

What are some common challenges faced by Junior RTL Design Engineers when transitioning from academic projects to industry roles?

Junior RTL Design Engineers often find the transition from academic projects to industry roles challenging due to the increased complexity and scale of commercial designs. In industry, there is a strong emphasis on meeting strict timing, power, and area requirements, as well as adhering to rigorous verification and documentation standards. Collaboration with verification, physical design, and software teams is essential, and juniors may need to quickly adapt to using industry-standard EDA tools and workflows. Gaining proficiency in debugging and understanding legacy codebases are also typical hurdles. However, most teams provide mentorship and structured onboarding to help new engineers succeed.

What are Junior RTL Design Engineers?

Junior RTL Design Engineers are entry-level professionals who work on designing and verifying the Register Transfer Level (RTL) logic for digital integrated circuits. They typically use hardware description languages like Verilog or VHDL to describe and simulate the functionality of hardware blocks according to specifications. Their responsibilities often include coding, simulation, debugging, and collaborating with senior engineers to ensure the design meets performance and functional requirements. This role is crucial in the process of creating chips and digital systems used in various electronic devices.

What is the difference between Junior Rtl Design Engineer vs Digital Design Engineer?

AspectJunior Rtl Design EngineerDigital Design Engineer
Required CredentialsBachelor's in Electrical Engineering or related field; some certificationsBachelor's or higher in Electrical/Electronic Engineering; certifications vary
Work EnvironmentDesign teams in semiconductor or electronics companiesDesign and development teams in similar industries
Employer & Industry UsageCommonly employed in chip design, FPGA, ASIC developmentUsed in digital circuit and system design across industries

Both roles involve digital circuit design, but Junior Rtl Design Engineers focus more on RTL coding and verification, while Digital Design Engineers may handle broader digital system development. The roles often overlap in skills and work environment, with the main difference being scope and experience level.

What job categories do people searching Junior Rtl Design Engineer jobs in Ohio look for? The top searched job categories for Junior Rtl Design Engineer jobs in Ohio are:
What cities in Ohio are hiring for Junior Rtl Design Engineer jobs? Cities in Ohio with the most Junior Rtl Design Engineer job openings:
Infographic showing various Junior Rtl Design Engineer job openings in Ohio as of May 2026, with employment types broken down into 100% Full Time. Highlights an 100% In-person job distribution, with an average salary of $68,259 per year, or $32.8 per hour.
Programmable Logic Design Engineer

Programmable Logic Design Engineer

Viasat, Inc.

Independence, OH

$193.50K - $290.50K/yr

Contractor

Posted 28 days ago


Viasat rating

3.4

Company rating: 3.4 out of 10

Based on 6 frontline employees who took The Breakroom Quiz

76th of 76 rated telecommunications companies


Job description

About us

One team. Global challenges. Infinite opportunities. At Viasat, we’re on a mission to deliver connections with the capacity to change the world. For more than 35 years, Viasat has helped shape how consumers, businesses, governments and militaries around the globe communicate. We’re looking for people who think big, act fearlessly, and create an inclusive environment that drives positive impact to join our team.


What you'll do

In this role you will help develop high speed signal processing algorithms and/or network protocols in FPGAs. The individual will be responsible for the full design phase starting from the requirements' phase to documentation, block diagrams, implementation of source code, simulation, place & route, testing in hardware, and integration.


The day-to-day
  • Collaborate with team members to jointly develop high-speed digital signal processing and waveform processing algorithms supporting satellite communications applications
  • Develop testbenches and help maintain and update system level verification environment
  • Synthesize Verilog and System Verilog for Xilinx/AMD FPGAs
  • Develop timing constraints, analyze timing results, and implement design changes required to close timing
  • Generate and collaborate on required design documents, development requirements, specifications and verification protocols
  • Responsible for owning and driving technical issues to resolution
  • Integrate and debugs design in the laboratory

What you'll need
  • Bachelor's Degree in Electrical Engineering, Computer Engineering or a related field
  • 5-8 years FPGA design experience, including Xilinx Vivado
  • Strong knowledge of System Verilog
  • Experience with RTL design for various signal processing blocks, including but not limited to equalizers, correlators, filters, FEC encoders and decoders
  • Proven track record to design and implement FPGA modules using System Verilog with simulation and testbench development
  • Work independently, take initiative, and take ownership of tasks and results
  • Strong written and verbal communication skills, ability to work with a geographically distributed team

What will help you on the job
  • Familiarity with Matlab
  • Experience with GitHub
  • Experience with developing code for legacy Viasat modem platforms
  • Familiarity with DVB-S2x and DVB-RCS2 standards
  • Understanding and knowledge of Satellite communication waveforms and standards

#LI-BBS


Salary range
$155,500.00 - $246,000.00 / annually.For specific work locations within San Jose, the San Francisco Bay area and New York City metropolitan area, the base pay range for this role is $193,500.00- $290,500.00/ annually
At Viasat, we consider many factors when it comes to compensation, including the scope of the position as well as your background and experience. Base pay may vary depending on job-related knowledge, skills, and experience. Additional cash or stock incentives may be provided as part of the compensation package, in addition to a range of medical, financial, and/or other benefits, dependent on the position offered. Learn more about Viasat's comprehensive benefit offerings that are focused on your holistic health and wellness at https://careers.viasat.com/benefits.
EEO Statement

Viasat is proud to be an equal opportunity employer, seeking to create a welcoming and diverse environment. All qualified applicants will receive consideration for employment without regard to race, color, religion, gender, gender identity or expression, sexual orientation, national origin, ancestry, physical or mental disability, medical condition, marital status, genetics, age, or veteran status or any other applicable legally protected status or characteristic. If you would like to request an accommodation on the basis of disability for completing this on-line application, please click here.

Qualifications:
  • Bachelor's Degree in Electrical Engineering, Computer Engineering or a related field
  • 5-8 years FPGA design experience, including Xilinx Vivado
  • Strong knowledge of System Verilog
  • Experience with RTL design for various signal processing blocks, including but not limited to equalizers, correlators, filters, FEC encoders and decoders
  • Proven track record to design and implement FPGA modules using System Verilog with simulation and testbench development
  • Work independently, take initiative, and take ownership of tasks and results
  • Strong written and verbal communication skills, ability to work with a geographically distributed team
Education:UNAVAILABLEEmployment Type: CONTRACTOR

ViaSat logo

About ViaSat

Sourced by ZipRecruiter

At Viasat, we're on a mission to deliver connections with the capacity to change the world. For more than 35 years, Viasat has helped shape how consumers, businesses, governments and militaries around the globe communicate.

Industry

Telecommunications

Company size

5,001 - 10,000 Employees

Headquarters location

Carlsbad, CA, US

Year founded

1986