Senior Design Verification Engineer
$193K - $290K/yr
As a Design Verification Engineer, you will be part of a verification team responsible for the full cycle of RTL verification for FPGA and ASIC designs. You will be responsible for: * Design ...
Senior Design Verification Engineer
$193K - $290K/yr
As a Design Verification Engineer, you will be part of a verification team responsible for the full cycle of RTL verification for FPGA and ASIC designs. You will be responsible for: * Design ...
Associate, FPGA / ASIC Verification Engineer
Cincinnati, OH · On-site
$118K - $162K/yr
Employees work 10 hour days, 4 days a week As an Associate ASIC/FPGA Verification Engineer at L3Harris you will be responsible for verifying the architecture, design and implementation of next ...
Associate, FPGA / ASIC Verification Engineer
Cincinnati, OH · On-site
$118K - $162K/yr
Employees work 10 hour days, 4 days a week As an Associate ASIC/FPGA Verification Engineer at L3Harris you will be responsible for verifying the architecture, design and implementation of next ...
Microelectronics Design and Verification Engineer
Beavercreek, OH · On-site +1
$126K - $154K/yr
You Have: * 20+ years of experience working within FPGA and ASIC design * Experience in integrated ... engineering * Experience with EDA tools supporting IC design, verification, testing, or physical ...
Microelectronics Design and Verification Engineer
Beavercreek, OH · On-site +1
$126K - $154K/yr
You Have: * 20+ years of experience working within FPGA and ASIC design * Experience in integrated ... engineering * Experience with EDA tools supporting IC design, verification, testing, or physical ...
Microelectronics Design and Verification Engineer
Beavercreek, OH · On-site
$99K - $225K/yr
You Have: * 20+ years of experience working within FPGA and ASIC design * Experience in integrated ... engineering * Experience with EDA tools supporting IC design, verification, testing, or physical ...
Microelectronics Design and Verification Engineer
Beavercreek, OH · On-site
$99K - $225K/yr
You Have: * 20+ years of experience working within FPGA and ASIC design * Experience in integrated ... engineering * Experience with EDA tools supporting IC design, verification, testing, or physical ...
Microelectronics Design and Verification Engineer
Beavercreek, OH · On-site
$99K - $225K/yr
You Have: * 20+ years of experience working within FPGA and ASIC design * Experience in integrated ... engineering * Experience with EDA tools supporting IC design, verification, testing, or physical ...
Microelectronics Design and Verification Engineer
Beavercreek, OH · On-site
$99K - $225K/yr
You Have: * 20+ years of experience working within FPGA and ASIC design * Experience in integrated ... engineering * Experience with EDA tools supporting IC design, verification, testing, or physical ...
Microelectronics Design and Verification Engineer
Beavercreek, OH · On-site
$99K - $225K/yr
You Have: * 20+ years of experience working within FPGA and ASIC design * Experience in integrated ... engineering * Experience with EDA tools supporting IC design, verification, testing, or physical ...
Microelectronics Design and Verification Engineer
Beavercreek, OH · On-site
$99K - $225K/yr
You Have: * 20+ years of experience working within FPGA and ASIC design * Experience in integrated ... engineering * Experience with EDA tools supporting IC design, verification, testing, or physical ...
Microelectronics Design and Verification Engineer
Beavercreek, OH · On-site
$99K - $225K/yr
You Have: * 20+ years of experience working within FPGA and ASIC design * Experience in integrated ... engineering * Experience with EDA tools supporting IC design, verification, testing, or physical ...
Microelectronics Design and Verification Engineer
Beavercreek, OH · On-site
$99K - $225K/yr
You Have: * 20+ years of experience working within FPGA and ASIC design * Experience in integrated ... engineering * Experience with EDA tools supporting IC design, verification, testing, or physical ...
You Have: * 20+ years of experience working within FPGA and ASIC design * Experience in integrated ... engineering * Experience with EDA tools supporting IC design, verification, testing, or physical ...
You Have: * 20+ years of experience working within FPGA and ASIC design * Experience in integrated ... engineering * Experience with EDA tools supporting IC design, verification, testing, or physical ...
Microelectronics Design and Verification Engineer with Security Clearance
Alpha, OH · On-site
$99K - $225K/yr
You Have: * 20+ years of experience working within FPGA and ASIC design * Experience in integrated ... engineering * Experience with EDA tools supporting IC design, verification, testing, or physical ...
Microelectronics Design and Verification Engineer with Security Clearance
Alpha, OH · On-site
$99K - $225K/yr
You Have: * 20+ years of experience working within FPGA and ASIC design * Experience in integrated ... engineering * Experience with EDA tools supporting IC design, verification, testing, or physical ...
Associate, FPGA / ASIC Verification Engineer
Cincinnati, OH · On-site
$118K - $162K/yr
Associate, FPGA / ASIC Verification Engineer Job Code:40384 Job Location: Cincinnati, OH Job ... The primary responsibilities will focus on Verilog FPGA design verification, and the System Verilog ...
Associate, FPGA / ASIC Verification Engineer
Cincinnati, OH · On-site
$118K - $162K/yr
Associate, FPGA / ASIC Verification Engineer Job Code:40384 Job Location: Cincinnati, OH Job ... The primary responsibilities will focus on Verilog FPGA design verification, and the System Verilog ...
Specialist, FPGA/ASIC Hardware Engineer, Electrical Engineering Job Code: 41606 Job Location ... The primary responsibilities will focus on Verilog FPGA design, System Verilog UVM verification and ...
Specialist, FPGA/ASIC Hardware Engineer, Electrical Engineering Job Code: 41606 Job Location ... The primary responsibilities will focus on Verilog FPGA design, System Verilog UVM verification and ...
Specialist, FPGA/ASIC Hardware Engineer, Electrical Engineering Job Code: 41606 Job Location ... The primary responsibilities will focus on Verilog FPGA design, System Verilog UVM verification and ...
Specialist, FPGA/ASIC Hardware Engineer, Electrical Engineering Job Code: 41606 Job Location ... The primary responsibilities will focus on Verilog FPGA design, System Verilog UVM verification and ...
VHDL Design Engineer All candidates must be eligible to obtain a United States Security Clearance ... FPGA/ASIC architecture design, simulation and verification, MATLAB or C/C++ familiarity and ...
New
VHDL Design Engineer All candidates must be eligible to obtain a United States Security Clearance ... FPGA/ASIC architecture design, simulation and verification, MATLAB or C/C++ familiarity and ...
New
VHDL Design Engineer All candidates must be eligible to obtain a United States Security Clearance ... FPGA/ASIC architecture design, simulation and verification, MATLAB or C/C++ familiarity and ...
New
Quick apply
VHDL Design Engineer All candidates must be eligible to obtain a United States Security Clearance ... FPGA/ASIC architecture design, simulation and verification, MATLAB or C/C++ familiarity and ...
New
Hardware Verification Engineer (Solon)
Solon, OH · On-site
$114K - $151K/yr
Design and build test fixtures used in hardware validation. * Maintain and organize test equipment ... Internship or academic project experience related to hardware validation or testing. * Exposure to ...
Hardware Verification Engineer (Solon)
Solon, OH · On-site
$114K - $151K/yr
Design and build test fixtures used in hardware validation. * Maintain and organize test equipment ... Internship or academic project experience related to hardware validation or testing. * Exposure to ...
VHDL Design Engineer
Cincinnati, OH · On-site
$118K - $163K/yr
FPGA Design Engineer Note our client is based in Cincinnati, Ohio. Our client is willing to ... FPGA/ASIC architecture design, simulation and verification, MATLAB or C/C++ familiarity and ...
VHDL Design Engineer
Cincinnati, OH · On-site
$118K - $163K/yr
FPGA Design Engineer Note our client is based in Cincinnati, Ohio. Our client is willing to ... FPGA/ASIC architecture design, simulation and verification, MATLAB or C/C++ familiarity and ...
FPGA Electrical Engineer
Cincinnati, OH · On-site
... Design, logic design) LOCATION : Cincinnati, OH DURATION : Full-Time SALARY : Excellent ... ASIC / FPGA designs will include various sensor interfaces, sequence verification, A/D and D/A ...
FPGA Electrical Engineer
Cincinnati, OH · On-site
... Design, logic design) LOCATION : Cincinnati, OH DURATION : Full-Time SALARY : Excellent ... ASIC / FPGA designs will include various sensor interfaces, sequence verification, A/D and D/A ...
Senior FPGA Engineer #2730
$106K - $197K/yr
ASIC / FPGA designs will include various sensor interfaces, sequence verification, A/D and D/A ... The primary responsibilities will focus on Verilog FPGA design, System Verilog UVM verification and ...
Senior FPGA Engineer #2730
$106K - $197K/yr
ASIC / FPGA designs will include various sensor interfaces, sequence verification, A/D and D/A ... The primary responsibilities will focus on Verilog FPGA design, System Verilog UVM verification and ...
$96K - $141K/yr
... verification, working closely with the PM, Technical Lead, other CapDev engineers (SW, HW, RF, ME ... As part of modernization efforts, design test cases and procedures for commonality across test ...
$96K - $141K/yr
... verification, working closely with the PM, Technical Lead, other CapDev engineers (SW, HW, RF, ME ... As part of modernization efforts, design test cases and procedures for commonality across test ...
$96K - $141K/yr
... verification, working closely with the PM, Technical Lead, other CapDev engineers (SW, HW, RF, ME ... As part of modernization efforts, design test cases and procedures for commonality across test ...
$96K - $141K/yr
... verification, working closely with the PM, Technical Lead, other CapDev engineers (SW, HW, RF, ME ... As part of modernization efforts, design test cases and procedures for commonality across test ...
Asic Design Verification Engineer Internship information
What does an ASIC Design Verification Engineer Intern do?
An ASIC Design Verification Engineer Intern assists with testing and validating the functionality of Application-Specific Integrated Circuits (ASICs) during the hardware development process. Their responsibilities typically include writing test benches, developing verification environments, running simulations, and identifying bugs or design flaws before fabrication. Interns often use hardware description languages like Verilog or VHDL and verification methodologies such as UVM. This role is essential to ensure that the final ASIC design meets the required specifications and functions correctly.
What are the key skills and qualifications needed to thrive as an ASIC Design Verification Engineer Intern, and why are they important?
To thrive as an ASIC Design Verification Engineer Intern, you typically need a solid background in digital logic design, hardware description languages (HDLs) like Verilog or VHDL, and coursework in computer engineering or electrical engineering. Familiarity with simulation tools (such as ModelSim or Synopsys VCS), scripting languages like Python or Perl, and version control systems is highly valued. Strong analytical thinking, problem-solving abilities, and effective teamwork skills set exceptional candidates apart. These competencies are crucial for ensuring the functionality, reliability, and timely delivery of complex integrated circuits.
What are some typical challenges faced during an ASIC Design Verification Engineer Internship, and how can interns effectively address them?
Interns in ASIC design verification often encounter challenges such as understanding complex hardware specifications, learning new verification tools and methodologies, and debugging intricate design issues. To overcome these, it's important to proactively seek guidance from senior engineers, utilize available documentation and training resources, and actively participate in team meetings. Building strong communication skills and staying organized with test plans and bug tracking can also make the workflow smoother and more manageable.
What is the difference between Asic Design Verification Engineer Internship vs Asic Design Engineer?
| Aspect | Asic Design Verification Engineer Internship | Asic Design Engineer |
|---|---|---|
| Credentials | Typically pursuing or recent graduate in Electrical Engineering or Computer Engineering | Bachelor's or Master's degree in Electrical Engineering or related field |
| Work Environment | Internship program, often in a corporate R&D or design team | Full-time professional role in ASIC design teams |
| Responsibilities | Assisting in verification testbenches, running simulations, learning verification tools | Designing, implementing, and testing ASIC hardware components |
| Duration | Usually 3-6 months | Full-time ongoing role |
The Asic Design Verification Engineer Internship is an entry-level, temporary position focused on assisting verification tasks, while the Asic Design Engineer role involves full responsibility for ASIC design and development. Internships provide hands-on experience, whereas full engineers lead projects and make design decisions.
What are popular job titles related to Asic Design Verification Engineer Internship jobs in Ohio? For Asic Design Verification Engineer Internship jobs in Ohio, the most frequently searched job titles are:
What job categories do people searching Asic Design Verification Engineer Internship jobs in Ohio look for? The top searched job categories for Asic Design Verification Engineer Internship jobs in Ohio are:
What cities in Ohio are hiring for Asic Design Verification Engineer Internship jobs? Cities in Ohio with the most Asic Design Verification Engineer Internship job openings:
$193K - $290K/yr
Full-time
Re-posted 24 days ago
Viasat rating
6.3
Based on 11 frontline employees who took The Breakroom Quiz
78th of 96 rated telecommunications companies
Job description
About us
What you'll do
The day-to-day
What you'll need
What will help you on the job
Salary range
$155,500.00 - $246,000.00 / annually.For specific work locations within San Jose, the San Francisco Bay area and New York City metropolitan area, the base pay range for this role is $193,500.00- $290,500.00/ annually
At Viasat, we consider many factors when it comes to compensation, including the scope of the position as well as your background and experience. Base pay may vary depending on job-related knowledge, skills, and experience. Additional cash or stock incentives may be provided as part of the compensation package, in addition to a range of medical, financial, and/or other benefits, dependent on the position offered. Learn more about Viasat's comprehensive benefit offerings that are focused on your holistic health and wellness at https://careers.viasat.com/benefits.
EEO Statement
One team. Global challenges. Infinite opportunities. At Viasat, we’re on a mission to deliver connections with the capacity to change the world. For more than 35 years, Viasat has helped shape how consumers, businesses, governments and militaries around the globe communicate. We’re looking for people who think big, act fearlessly, and create an inclusive environment that drives positive impact to join our team.
What you'll do
At Viasat, you will be joining a talented and motivated team of systems engineers, design engineers, and design verification engineers developing cutting edge communications technology with a focus on high quality and time to market.
You will be working in a verification environment utilizing current tools and methodologies such as Universal Verification Methodology (UVM) and new DV AI agentic tools. You will be asked to help evaluate and deploy new technologies for design verification as they become available.
As a Design Verification Engineer, you will be part of a verification team responsible for the full cycle of RTL verification for FPGA and ASIC designs. You will be responsible for:
- Design verification planning including test plans
- Testbench development using SystemVerilog/UVM
- Hands-on debug with the design team
- Ensuring quality via collection and analysis of coverage metrics including code and functional coverage
- Managing regressions and compute resources
- Tool evaluation and license management
- Responsible for owning and driving technical issues to resolution
The day-to-day
Architecting Design Verification environments for ASICs and FPGAs.
Working with RTL, System and software engineers to determine appropriate coverage closure for chip designs.
Create drivers, monitors, scoreboards, sequences, and model predictors for a variety of interfaces and designs.
Maintaining and communicating program schedule and task tracking (Agile Jira based).
Debugging failing tests, understanding both the UVM testbench and VHDL/Verilog source code, working closely with the RTL developers.
What you'll need
- 8+ years Design Verification experience including UVM experience
Experience in UVM testbench creation and usage
Bachelor's Degree in Electrical Engineering, Computer Engineering or a related field
Experience with AI and agentic flow methodologies for design verification and chip development
Foundational knowledge of digital logic and timing considerations
Attention to detail, ability to follow process and coding guidelines, participate in code reviews and accept feedback
Experience with industry standard simulators such as Questa, Xcelium and VCS
Proven track record of work in UVM testbench development
US citizenship
Ability to travel up to 10%
- Must be able to obtain a secret clearance
What will help you on the job
Strong written and verbal communication skills, ability to work with a geographically distributed team
Object oriented programming experience
Familiarity with designing and coding for testbench horizontal and vertical re-use
Familiarity with AI coding agents for design verificaiton
Ability to work independently, take initiative, and take ownership of tasks and results
#LI-AF1
Salary range
$155,500.00 - $246,000.00 / annually.For specific work locations within San Jose, the San Francisco Bay area and New York City metropolitan area, the base pay range for this role is $193,500.00- $290,500.00/ annually
At Viasat, we consider many factors when it comes to compensation, including the scope of the position as well as your background and experience. Base pay may vary depending on job-related knowledge, skills, and experience. Additional cash or stock incentives may be provided as part of the compensation package, in addition to a range of medical, financial, and/or other benefits, dependent on the position offered. Learn more about Viasat's comprehensive benefit offerings that are focused on your holistic health and wellness at https://careers.viasat.com/benefits.
EEO Statement
Viasat is proud to be an equal opportunity employer, seeking to create a welcoming and diverse environment. All qualified applicants will receive consideration for employment without regard to race, color, religion, gender, gender identity or expression, sexual orientation, national origin, ancestry, physical or mental disability, medical condition, marital status, genetics, age, or veteran status or any other applicable legally protected status or characteristic. If you would like to request an accommodation on the basis of disability for completing this on-line application, please click here.
Qualifications:- 8+ years Design Verification experience including UVM experience
Experience in UVM testbench creation and usage
Bachelor's Degree in Electrical Engineering, Computer Engineering or a related field
Experience with AI and agentic flow methodologies for design verification and chip development
Foundational knowledge of digital logic and timing considerations
Attention to detail, ability to follow process and coding guidelines, participate in code reviews and accept feedback
Experience with industry standard simulators such as Questa, Xcelium and VCS
Proven track record of work in UVM testbench development
US citizenship
Ability to travel up to 10%
- Must be able to obtain a secret clearance
About ViaSat
Sourced by ZipRecruiter
At Viasat, we're on a mission to deliver connections with the capacity to change the world. For more than 35 years, Viasat has helped shape how consumers, businesses, governments and militaries around the globe communicate.
Industry
Telecommunications
Company size
5,001 - 10,000 Employees
Headquarters location
Carlsbad, CA, US
Year founded
1986