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Ai Chip Design Rtl Jobs in Ohio (NOW HIRING)

NTT Ltd.

Define the supporting datacenter design: high-density power (50-140 kW/rack), direct-to-chip and rear-door liquid cooling, structured cabling for AI fabrics and modular deployment models across on ...

Nttlimited

Define the supporting datacenter design: high-density power (50-140 kW/rack), direct-to-chip and rear-door liquid cooling, structured cabling for AI fabrics and modular deployment models across on ...

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Ai Chip Design Rtl information

What is the difference between Ai Chip Design Rtl vs Ai Chip Verification Engineer?

AspectAi Chip Design RtlAi Chip Verification Engineer
Primary FocusDeveloping and implementing Register Transfer Level (RTL) code for AI chipsVerifying and validating RTL designs to ensure functionality
Skills RequiredHDL languages (Verilog/VHDL), digital design, FPGA/ASIC knowledgeSimulation, testbench creation, debugging, scripting skills
Work EnvironmentDesign teams, hardware development labs, EDA toolsVerification teams, simulation environments, test setups
CertificationsHardware design certifications, FPGA/ASIC trainingVerification methodologies, UVM, SystemVerilog certifications

While Ai Chip Design Rtl focuses on creating the hardware description code for AI chips, Ai Chip Verification Engineer ensures that the RTL design functions correctly through rigorous testing. Both roles require knowledge of HDL languages and work closely within hardware development teams, but their core responsibilities differ—design versus verification.

What are common challenges faced by AI Chip Design RTL engineers during the verification process?

AI Chip Design RTL engineers often encounter challenges in ensuring their designs meet complex functional and performance requirements, especially given the rapid pace of AI hardware advancements. Verification can be particularly demanding due to the need to simulate and test intricate AI workloads, manage large datasets, and debug subtle timing or logic errors. Collaboration with verification teams, system architects, and software engineers is essential to address these issues efficiently and to ensure seamless integration of the RTL code into the broader chip design. Staying up-to-date with the latest verification tools and methodologies is also crucial for success in this role.

What is an AI Chip Design RTL engineer?

AI Chip Design RTL (Register Transfer Level) engineers are specialists who design the digital logic for chips used in artificial intelligence applications. They use hardware description languages like Verilog or VHDL to create and validate the architecture and functionality of these chips before they are manufactured. Their work ensures that AI processors are efficient, high-performing, and meet the requirements of modern AI workloads. RTL engineers collaborate closely with verification, software, and hardware teams to optimize chip performance and power consumption.

What skills and qualifications are needed to thrive as an AI Chip Design RTL engineer?

To thrive as an AI Chip Design RTL Engineer, you need a solid background in digital design, computer architecture, and proficiency in Hardware Description Languages (HDLs) like Verilog or VHDL, often supported by a degree in electrical or computer engineering. Experience with simulation tools (e.g., ModelSim, Synopsys), ASIC/FPGA design flows, and relevant certifications are highly valued. Strong problem-solving abilities, attention to detail, and effective teamwork and communication skills help you excel in collaborative and complex design environments. These competencies are crucial for creating efficient, reliable AI hardware that meets performance and power requirements in a fast-evolving field.
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Senior Design Verification Engineer

Viasat, Inc.

Independence, OH • On-site

$193K - $290K/yr

Full-time

Re-posted 26 days ago

Viasat rating

6.3

Company rating: 6.3 out of 10

Based on 11 frontline employees who took The Breakroom Quiz

78th of 96 rated telecommunications companies

Job description

About us

One team. Global challenges. Infinite opportunities. At Viasat, we’re on a mission to deliver connections with the capacity to change the world. For more than 35 years, Viasat has helped shape how consumers, businesses, governments and militaries around the globe communicate. We’re looking for people who think big, act fearlessly, and create an inclusive environment that drives positive impact to join our team.


What you'll do

At Viasat, you will be joining a talented and motivated team of systems engineers, design engineers, and design verification engineers developing cutting edge communications technology with a focus on high quality and time to market. 

You will be working in a verification environment utilizing current tools and methodologies such as Universal Verification Methodology (UVM) and new DV AI agentic tools.  You will be asked to help evaluate and deploy new technologies for design verification as they become available.

As a Design Verification Engineer, you will be part of a verification team responsible for the full cycle of RTL verification for FPGA and ASIC designs.  You will be responsible for:

  • Design verification planning including test plans
  • Testbench development using SystemVerilog/UVM
  • Hands-on debug with the design team
  • Ensuring quality via collection and analysis of coverage metrics including code and functional coverage
  • Managing regressions and compute resources
  • Tool evaluation and license management
  • Responsible for owning and driving technical issues to resolution

The day-to-day

  • Architecting Design Verification environments for ASICs and FPGAs.  

  • Working with RTL, System and software engineers to determine appropriate coverage closure for chip designs.

  • Create drivers, monitors, scoreboards, sequences, and model predictors for a variety of interfaces and designs.

  • Maintaining and communicating program schedule and task tracking (Agile Jira based).

  • Debugging failing tests, understanding both the UVM testbench and VHDL/Verilog source code, working closely with the RTL developers.


What you'll need
  • 8+ years Design Verification experience including UVM experience

  • Experience in UVM testbench creation and usage

  • Bachelor's Degree in Electrical Engineering, Computer Engineering or a related field

  • Experience with AI and agentic flow methodologies for design verification and chip development

  • Foundational knowledge of digital logic and timing considerations

  • Attention to detail, ability to follow process and coding guidelines, participate in code reviews and accept feedback

  • Experience with industry standard simulators such as Questa, Xcelium and VCS

  • Proven track record of work in UVM testbench development

  • US citizenship

  • Ability to travel up to 10%

  • Must be able to obtain a secret clearance

What will help you on the job

  • Strong written and verbal communication skills, ability to work with a geographically distributed team

  • Object oriented programming experience

  • Familiarity with designing and coding for testbench horizontal and vertical re-use

  • Familiarity with AI coding agents for design verificaiton

  • Ability to work independently, take initiative, and take ownership of tasks and results

#LI-AF1 


Salary range
$155,500.00 - $246,000.00 / annually.For specific work locations within San Jose, the San Francisco Bay area and New York City metropolitan area, the base pay range for this role is $193,500.00- $290,500.00/ annually
At Viasat, we consider many factors when it comes to compensation, including the scope of the position as well as your background and experience. Base pay may vary depending on job-related knowledge, skills, and experience. Additional cash or stock incentives may be provided as part of the compensation package, in addition to a range of medical, financial, and/or other benefits, dependent on the position offered. Learn more about Viasat's comprehensive benefit offerings that are focused on your holistic health and wellness at https://careers.viasat.com/benefits.
EEO Statement

Viasat is proud to be an equal opportunity employer, seeking to create a welcoming and diverse environment. All qualified applicants will receive consideration for employment without regard to race, color, religion, gender, gender identity or expression, sexual orientation, national origin, ancestry, physical or mental disability, medical condition, marital status, genetics, age, or veteran status or any other applicable legally protected status or characteristic. If you would like to request an accommodation on the basis of disability for completing this on-line application, please click here.

Qualifications:
  • 8+ years Design Verification experience including UVM experience

  • Experience in UVM testbench creation and usage

  • Bachelor's Degree in Electrical Engineering, Computer Engineering or a related field

  • Experience with AI and agentic flow methodologies for design verification and chip development

  • Foundational knowledge of digital logic and timing considerations

  • Attention to detail, ability to follow process and coding guidelines, participate in code reviews and accept feedback

  • Experience with industry standard simulators such as Questa, Xcelium and VCS

  • Proven track record of work in UVM testbench development

  • US citizenship

  • Ability to travel up to 10%

  • Must be able to obtain a secret clearance
Education:UNAVAILABLEEmployment Type: FULL_TIME

What Viasat employees say

Pay

Benefits

Hours and flexibility

Workplace

Get the full story on Breakroom

ViaSat logo

About ViaSat

Sourced by ZipRecruiter

At Viasat, we're on a mission to deliver connections with the capacity to change the world. For more than 35 years, Viasat has helped shape how consumers, businesses, governments and militaries around the globe communicate.

Industry

Telecommunications

Company size

5,001 - 10,000 Employees

Headquarters location

Carlsbad, CA, US

Year founded

1986

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