ASIC / FPGA designs will include various sensor interfaces, sequence verification, A/D and D/A ... Analysis of the requirements, architecture definition, design and debug of FPGA and associated ...
ASIC / FPGA designs will include various sensor interfaces, sequence verification, A/D and D/A ... Analysis of the requirements, architecture definition, design and debug of FPGA and associated ...
Senior FPGA Engineer
Cincinnati, OH · On-site
$106K - $197K/yr
ASIC / FPGA designs will include various sensor interfaces, sequence verification, A/D and D/A ... The primary responsibilities will focus on Verilog FPGA design, System Verilog UVM verification and ...
Senior FPGA Engineer
Cincinnati, OH · On-site
$106K - $197K/yr
ASIC / FPGA designs will include various sensor interfaces, sequence verification, A/D and D/A ... The primary responsibilities will focus on Verilog FPGA design, System Verilog UVM verification and ...
FPGA Engineer
$124K - $160K/yr
Description Apply Now RTL, C/C++, Python, VHDL, Verilog, Tcl, cryptography, hardware, embedded ... Key Responsibilities FPGA Design and Development: Design and develop IP cores and FPGA ...
FPGA Engineer
$124K - $160K/yr
Description Apply Now RTL, C/C++, Python, VHDL, Verilog, Tcl, cryptography, hardware, embedded ... Key Responsibilities FPGA Design and Development: Design and develop IP cores and FPGA ...
ASIC / FPGA designs will include various sensor interfaces, sequence verification, A/D and D/A ... Analysis of the requirements, architecture definition, design and debug of FPGA and associated ...
ASIC / FPGA designs will include various sensor interfaces, sequence verification, A/D and D/A ... Analysis of the requirements, architecture definition, design and debug of FPGA and associated ...
Senior FPGA Engineer
Dayton, OH · Hybrid
$116K - $153K/yr
The engineer is responsible for implementing complex digital signal processing (DSP) algorithms ... Transfer Level (RTL) architecture. * IP Development: Design, implement, and test custom ...
Senior FPGA Engineer
Dayton, OH · Hybrid
$116K - $153K/yr
The engineer is responsible for implementing complex digital signal processing (DSP) algorithms ... Transfer Level (RTL) architecture. * IP Development: Design, implement, and test custom ...
Senior FPGA Engineer
Dayton, OH · On-site
$116K - $153K/yr
The engineer is responsible for implementing complex digital signal processing (DSP) algorithms ... Transfer Level (RTL) architecture. * IP Development: Design, implement, and test custom ...
Quick apply
Senior FPGA Engineer
Dayton, OH · On-site
$116K - $153K/yr
The engineer is responsible for implementing complex digital signal processing (DSP) algorithms ... Transfer Level (RTL) architecture. * IP Development: Design, implement, and test custom ...
Senior FPGA Engineer
Dayton, OH · Hybrid
$116K - $153K/yr
The engineer is responsible for implementing complex digital signal processing (DSP) algorithms ... Transfer Level (RTL) architecture. * IP Development: Design, implement, and test custom ...
Senior FPGA Engineer
Dayton, OH · Hybrid
$116K - $153K/yr
The engineer is responsible for implementing complex digital signal processing (DSP) algorithms ... Transfer Level (RTL) architecture. * IP Development: Design, implement, and test custom ...
Apart from designing industry-leading ASIC chips and manufacturing mining rigs, the Group handles ... This includes equipment procurement, transport logistics, datacenter design and construction ...
Apart from designing industry-leading ASIC chips and manufacturing mining rigs, the Group handles ... This includes equipment procurement, transport logistics, datacenter design and construction ...
AI & Cloud Infra Software Engineer (Fresh Grad)
Massillon, OH · On-site
$54 - $70.25/hr
Apart from designing industry-leading ASIC chips and manufacturing mining rigs, the Group handles ... Design and build distributed systems for cluster management, scheduling, and resource allocation
Quick apply
AI & Cloud Infra Software Engineer (Fresh Grad)
Massillon, OH · On-site
$54 - $70.25/hr
Apart from designing industry-leading ASIC chips and manufacturing mining rigs, the Group handles ... Design and build distributed systems for cluster management, scheduling, and resource allocation
AI & Cloud Infra Software Engineer (Fresh Grad)
Massillon, OH · On-site
$54.75 - $71.25/hr
Apart from designing industry-leading ASIC chips and manufacturing mining rigs, the Group handles ... Design and build distributed systems for cluster management, scheduling, and resource allocation
AI & Cloud Infra Software Engineer (Fresh Grad)
Massillon, OH · On-site
$54.75 - $71.25/hr
Apart from designing industry-leading ASIC chips and manufacturing mining rigs, the Group handles ... Design and build distributed systems for cluster management, scheduling, and resource allocation
AI & Cloud Infra Software Engineer (Fresh Grad)
$54 - $70.25/hr
Apart from designing industry-leading ASIC chips and manufacturing mining rigs, the Group handles ... Design and build distributed systems for cluster management, scheduling, and resource allocation
AI & Cloud Infra Software Engineer (Fresh Grad)
$54 - $70.25/hr
Apart from designing industry-leading ASIC chips and manufacturing mining rigs, the Group handles ... Design and build distributed systems for cluster management, scheduling, and resource allocation
FPGA Developer
$99K - $225K/yr
... engineer with a background in Field Programmable Gate Array (FPGA) design, you will help solve ... Experience with EDA tools for HDL and RTL simulation, such as ModelSim, Questa, Xcelium, VCS, or ...
FPGA Developer
$99K - $225K/yr
... engineer with a background in Field Programmable Gate Array (FPGA) design, you will help solve ... Experience with EDA tools for HDL and RTL simulation, such as ModelSim, Questa, Xcelium, VCS, or ...
FPGA Developer
Wright-patterson Air Force Base, OH
$99K - $225K/yr
... engineer with a background in Field Programmable Gate Array (FPGA) design, you will help solve ... Experience with EDA tools for HDL and RTL simulation, such as ModelSim, Questa, Xcelium, VCS, or ...
FPGA Developer
Wright-patterson Air Force Base, OH
$99K - $225K/yr
... engineer with a background in Field Programmable Gate Array (FPGA) design, you will help solve ... Experience with EDA tools for HDL and RTL simulation, such as ModelSim, Questa, Xcelium, VCS, or ...
FPGA Developer
Beavercreek, OH · Hybrid
$99K - $225K/yr
... engineer with a background in Field Programmable Gate Array (FPGA) design, you will help solve ... Experience with EDA tools for HDL and RTL simulation, such as ModelSim, Questa, Xcelium, VCS, or ...
FPGA Developer
Beavercreek, OH · Hybrid
$99K - $225K/yr
... engineer with a background in Field Programmable Gate Array (FPGA) design, you will help solve ... Experience with EDA tools for HDL and RTL simulation, such as ModelSim, Questa, Xcelium, VCS, or ...
FPGA Developer
$99K - $225K/yr
... engineer with a background in Field Programmable Gate Array (FPGA) design, you will help solve ... Experience with EDA tools for HDL and RTL simulation, such as ModelSim, Questa, Xcelium, VCS, or ...
FPGA Developer
$99K - $225K/yr
... engineer with a background in Field Programmable Gate Array (FPGA) design, you will help solve ... Experience with EDA tools for HDL and RTL simulation, such as ModelSim, Questa, Xcelium, VCS, or ...
Drive design decisions and establish engineering standards (code quality, testing strategy, CI/CD ... TypeScript; modern React patterns; UI testing (Jest/RTL/Cypress). * Python frameworks (FastAPI ...
Drive design decisions and establish engineering standards (code quality, testing strategy, CI/CD ... TypeScript; modern React patterns; UI testing (Jest/RTL/Cypress). * Python frameworks (FastAPI ...
Drive design decisions and establish engineering standards (code quality, testing strategy, CI/CD ... TypeScript; modern React patterns; UI testing (Jest/RTL/Cypress). * Python frameworks (FastAPI ...
Drive design decisions and establish engineering standards (code quality, testing strategy, CI/CD ... TypeScript; modern React patterns; UI testing (Jest/RTL/Cypress). * Python frameworks (FastAPI ...
... design decisions and establish engineering standards (code quality, testing strategy, CI/CD ... Preferred : • TypeScript; modern React patterns; UI testing (Jest/RTL/Cypress). • Python ...
... design decisions and establish engineering standards (code quality, testing strategy, CI/CD ... Preferred : • TypeScript; modern React patterns; UI testing (Jest/RTL/Cypress). • Python ...
Drive design decisions and establish engineering standards (code quality, testing strategy, CI/CD ... TypeScript; modern React patterns; UI testing (Jest/RTL/Cypress). * Python frameworks (FastAPI ...
Drive design decisions and establish engineering standards (code quality, testing strategy, CI/CD ... TypeScript; modern React patterns; UI testing (Jest/RTL/Cypress). * Python frameworks (FastAPI ...
Digital, analog, microprocessor, ASIC PCB design, EMI (Immunity and Emissions), Magnetics ... Real-time programming in Embedded C * Experience with Stage Gate project management * Experienced ...
Digital, analog, microprocessor, ASIC PCB design, EMI (Immunity and Emissions), Magnetics ... Real-time programming in Embedded C * Experience with Stage Gate project management * Experienced ...
Locum Asic Rtl Design Engineer information
What is the difference between Locum Asic Rtl Design Engineer vs Contract Asic Rtl Design Engineer?
| Aspect | Locum Asic Rtl Design Engineer | Contract Asic Rtl Design Engineer |
|---|---|---|
| Credentials | Typically requires relevant engineering degrees and RTL design experience | Similar credentials, often with specific RTL design certifications |
| Work Environment | Temporary, short-term assignments often in multiple locations | Project-based roles, usually in a fixed location or remote |
| Employer Usage | Used by agencies or companies needing immediate, short-term expertise | Engaged by companies or staffing agencies for project-specific work |
Both roles involve RTL design skills for ASIC development, but a Locum Asic Rtl Design Engineer typically fills short-term, temporary positions, often through staffing agencies, while a Contract Asic Rtl Design Engineer is engaged for specific projects with defined durations. The main difference lies in the nature and duration of employment, but both require similar technical credentials and work environments.
$106K - $197K/yr
Other
Medical, Retirement, PTO
Posted 20 days ago
Job description
Job Title: Senior Specialist, Electrical Engineering FPGA
Job Code: 33462
Job Location: Cincinnati, OH
Job Schedule: 4/10 - Employees work 10 hour days, 4 days per week.
Job Description:
As a Hardware Engineer at L3Harris you will be responsible for architecture, design and development of next generation Electronic Safe and Arm Devices utilizing the latest state of the art technologies. The ideal candidate for this role would share our passion for creating and innovating new technologies in a highly dynamic, fast-paced environment. We are looking for highly talented, motivated, and versatile engineers that can create the next generation fuzing solutions. ASIC / FPGA designs will include various sensor interfaces, sequence verification, A/D and D/A interfaces, communication protocols, state machines, timer chains, etc. used in Electronic Safe and Arm Devices (Fuzes) for DOD weapon systems. Microsemi / Actel is our targeted FPGA and QuestaSim is our simulation tool. The primary responsibilities will focus on Verilog FPGA design, System Verilog UVM verification and C# based microcontroller development.
Essential Functions:
- Analysis of the requirements, architecture definition, design and debug of FPGA and associated hardware and microcontroller products and associated firmware.
- Developing Verilog HDL targeting Antifuse and enhanced Flash FPGA's.
- Performing effective analysis of functional issues or performance profiling with the hardware and firmware in test environments or target host systems.
- Contribute to process improvements to ensure hardware-firmware quality and time-to-market.
Qualifications:
- Bachelor's Degree and minimum 6 years of prior relevant experience. Graduate Degree and a minimum of 4 years of prior related experience. In lieu of a degree, minimum of 10 years of prior related experience.
- Knowledge using Verilog for Logic Design.
- Programming experience in C for embedded systems, including development of algorithms, manipulation of data structures, and implementing highly optimized code.
- Experience with lab tools: Logic Analyzers, oscilloscopes, JTAG/ICE debuggers and protocol analyzers.
- Familiar with hardware, software and firmware development methodologies to ensure quality and time-to-market (design verification, code reviews, unit testing, prototyping and product testing).
- Familiar working with code version control repository tools, such as Subversion (SVN), GIT or TFS.
- Digital Design practices and principles, logic design and architecture and experience with HDL's (i.e Verilog, VHDL).
Preferred Additional Skills:
- Knowledge using SystemVerilog for verification with AVM, VMM, OVM, or UVM a plus.
- Developing C# source code targeting enhanced Flash Microcontrollers.
- Good English knowledge (speech and writing).
- Be action-oriented and organized.
- Ability to handle short notice needs/requests.
In compliance with pay transparency requirements, the salary range for this role in California, Massachusetts, New Jersey, Washington, and the Greater D.C, Denver, or NYC areas is $106,500 - $197,500. The salary range for this role in Colorado state, Hawaii, Illinois, Maryland, Minnesota, New York state, Cleveland Ohio, and Vermont is $92,500 - $171,500. This is not a guarantee of compensation or salary, as final offer amount may vary based on factors including but not limited to experience and geographic location. L3Harris also offers a variety of benefits, including health and disability insurance, 401(k) match, flexible spending accounts, EAP, education assistance, parental leave, paid time off, and company-paid holidays. The specific programs and options available to an employee may vary depending on date of hire, schedule type, and the applicability of collective bargaining agreements.
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